Stacked Semiconductor Package With Intermediate Circuit Layers
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Solution Overview
Problem
The yield rate of stacked semiconductor device modules is a significant issue due to electrical connection challenges, particularly during the heating process, where short-circuits can occur, affecting the reliability of the semiconductor device package.
Innovation Solution
Incorporating a first and second intermediate circuit layer between the semiconductor modules, with conductive vias connecting the modules to prevent short-circuits and enhance electrical connections, ensuring both surfaces of the intermediate circuit layers are free from electronic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If modules are directly stacked without intermediate circuit layers, then device complexity is reduced, but electrical connection reliability deteriorates due to short-circuit risks during heating
Solution Approach 1:
The patent introduces intermediate circuit layers as mediator components between stacked semiconductor modules. These intermediate layers provide isolated connection points and conductive vias that mediate electrical connections while preventing direct contact between opposing module surfaces, thereby eliminating short-circuit risks during thermal processing while maintaining connection reliability.
Solution Approach 2:
The patent segments the direct interface between stacked modules by inserting intermediate circuit layers. This segmentation divides the electrical connection path into multiple isolated stages, allowing each module to connect to the intermediate layer through controlled conductive vias rather than direct module-to-module contact, thus preventing short-circuits while enabling reliable connections.
2Reliability
If intermediate circuit layers with electronic components are used, then electrical connection reliability improves, but manufacturing complexity and yield rate worsen due to additional component mounting
Solution Approach 1:
The patent extracts electronic components from the intermediate circuit layers, creating component-free intermediate layers that serve solely as connection mediators. This extraction eliminates the need for component mounting and inspection on intermediate layers, thereby maintaining electrical connection reliability through controlled conductive vias while significantly improving manufacturing yield rate by reducing process complexity.
3Productivity
If modules are directly stacked, then manufacturing process is simplified, but short-circuits occur during heating process affecting yield rate
Solution Approach 1:
The intermediate circuit layers act as thermal and electrical mediators during the heating process. They provide controlled conductive paths through isolated vias that prevent uncontrolled current flow and short-circuits between stacked modules, thereby eliminating the harmful short-circuit effect while maintaining a streamlined manufacturing process that improves yield rate.
Solution Approach 2:
The patent implements prior cushioning by pre-designing the intermediate circuit layers with controlled conductive vias and isolation structures before the stacking and heating processes. This pre-configured protection cushions against potential short-circuit hazards during thermal processing, ensuring manufacturing reliability and improving yield rate without complicating the overall manufacturing flow.
Data Source
AI summary
A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first module, a second module, a first intermediate circuit layer, a first conductive transmission path and a second conductive transmission path. The second module is stacked on the first module. The first intermediate circuit layer is arranged between the first module and the second module. The first conductive transmission is configured to electrically connect the first semiconductor module with the first intermediate circuit layer. The second conductive transmission path is configured to electrically connect the first intermediate circuit layer with the second semiconductor module.