Stacked Semiconductor Package with Interposer Leads
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Solution Overview
Problem
Conventional semiconductor devices face challenges in efficiently stacking semiconductor chips to reduce size and weight while maintaining effective electrical connections for multi-chip packages, particularly in achieving a cost-effective and reliable method for both sides stacked lead frame structures.
Innovation Solution
A stacked package structure for semiconductor devices is proposed, featuring at least one first semiconductor chip, a second semiconductor chip, and a third semiconductor chip, with interposer leads providing electrical connections between them, and external connection leads connecting the third chip to the outside, using a wire bonding unit to connect all chips and leads, and a molding resin to cover the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If semiconductor chips are stacked on both sides to reduce size and weight, then the size and weight of the semiconductor device are reduced, but the complexity of electrical connections and manufacturing process increases
Solution Approach 1:
The patent introduces a lead frame as an intermediary structure that provides pre-formed electrical connection paths between chips stacked on both sides. The lead frame acts as a mediator that simplifies the complex electrical interconnections by providing a structured framework with integrated bonding pads and connection leads, eliminating the need for complex wire bonding networks while enabling both-side chip stacking.
Solution Approach 2:
The patent divides the electrical connection system into separate functional segments: bonding pads on the lead frame for chip connections, connection leads for external connections, and mold resin for structural support. This segmentation allows each component to be optimized independently and simplifies the overall manufacturing process by enabling modular assembly of chips on both sides of the lead frame.
2Volume of moving object
If a multi-chip package structure is used to reduce size, then the device size is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The lead frame is prepared in advance with pre-formed bonding pads and connection leads positioned at precise locations before chip stacking. This preliminary preparation of the lead frame structure provides fixed reference points that guide chip placement and reduce the precision requirements during the actual chip stacking process, as the lead frame already establishes the correct spatial relationships.
Solution Approach 2:
The lead frame serves as an intermediary structure that absorbs and compensates for dimensional variations and misalignments between chips. By providing a rigid framework with pre-positioned bonding pads, the lead frame mediates the tolerance accumulation that would otherwise occur during multi-chip stacking, reducing the overall manufacturing precision requirements.
3Productivity
If chips are stacked on both sides of the lead frame, then productivity increases, but the reliability of electrical connections decreases
Solution Approach 1:
The patent merges the electrical connection function with the structural support function into a single lead frame component. The lead frame simultaneously provides mechanical support for chips on both sides and establishes all electrical connections through its integrated bonding pads and connection leads. This merging reduces the number of separate components and connection interfaces, thereby improving reliability while enabling high-density chip stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables effective stacking of semiconductor chips on both surfaces, reducing size and weight, while ensuring reliable electrical connections and cost-effective manufacturing by using interposer leads and wire bonding, thus addressing the challenges of conventional semiconductor device packaging.
Implementation Method 1
a wire bonding unit electrically connecting the at least one first semiconductor chip, the at least one second semiconductor chip, the third semiconductor chip, the at least one interposer lead, and the external connection leads to each other
Implementation Method 2
covering the at least one first semiconductor chip, the at least one second semiconductor chip, the at least one third semiconductor chip, the at least one interposer lead, and at least a portion of the external connection lead with a mold material
Data Source
AI summary
Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside.