Stacked Semiconductor Package with Matching Dielectric Layers
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Solution Overview
Problem
The challenge in semiconductor device packaging is the undesired configurations of integrated components post-curing, leading to yield loss, poor bonding, cracking, and delamination due to differences in thermal properties, which complicates manufacturing and increases the risk of popcorn issues during reflow operations.
Innovation Solution
A semiconductor package assembly is developed with a wafer-level packaging design, utilizing a first and second dielectric layer composed of low-temperature polyimide with matching thermal expansion coefficients, along with conductive bumps and vias, where the second dielectric layer has holes drilled by laser to optimize underfill capillarity and reduce void ratios, ensuring reliable attachment and minimizing material costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple integrated components with different thermal properties are vertically coupled to increase component density, then device integration and component density are improved, but thermal expansion mismatch causes undesired configurations, cracking, and delamination
Solution Approach 1:
The patent introduces an underfill material as an intermediary substance between stacked semiconductor components. This underfill material has thermal expansion properties that match the surrounding components, acting as a buffer that absorbs thermal stress during reflow operations. The underfill prevents direct thermal stress transmission between components with mismatched thermal expansion coefficients, thereby preventing cracking and delamination while maintaining vertical coupling for high density.
Solution Approach 2:
The patent modifies the thermal expansion parameter by selecting materials with specific thermal expansion coefficients that match adjacent components. The dielectric layers and underfill materials are chosen to have thermal expansion coefficients that closely match the semiconductor dies and interconnect structures, creating a thermally compatible stack that minimizes stress during temperature cycling and reflow processes.
2Productivity
If complex manufacturing operations are performed to achieve high integration, then device functionality and density are improved, but manufacturing complexity increases making structural modification difficult
Solution Approach 1:
The patent applies underfill material to the substrate before stacking the semiconductor components. This preliminary action ensures that the thermal stress buffer is already in place before the components are bonded together, simplifying the manufacturing process. By pre-applying the underfill, the patent avoids the need for complex post-assembly modifications and ensures proper material distribution before the components are irreversibly bonded.
Solution Approach 2:
The patent combines multiple functions into the underfill material application step: it serves as both a thermal stress buffer and a bonding adhesive, eliminating the need for separate stress-management layers or processes. The underfill material simultaneously provides mechanical support, thermal matching, and bonding functionality, reducing the overall number of manufacturing steps and materials required.
3Ease of manufacture
If conventional packaging methods are used, then manufacturing simplicity is maintained, but popcorn issues and yield loss occur due to thermal stress
Solution Approach 1:
The underfill material serves as a protective intermediary between the solder joints and the external environment. During reflow operations, this underfill material absorbs and distributes thermal stress, preventing the sudden vaporization and expansion that causes popcorn defects. The underfill creates a controlled thermal environment that protects vulnerable solder joints from extreme thermal shock.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents popcorn issues by ensuring reliable attachment of conductive bumps to vias and reducing void ratios, enhancing the semiconductor device's reliability and reducing material costs through improved thermal stability and underfill fluidity.
Implementation Method 1
a plurality of holes are formed on the first dielectric layer to expose the via respectively
Implementation Method 2
utilizing a first and second dielectric layer composed of low-temperature polyimide with matching thermal expansion coefficients, along with conductive bumps and vias, where the second dielectric layer has holes drilled by laser to optimize underfill capillarity and reduce void ratios
Data Source
AI summary
A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.