Stacked Semiconductor Module Pad Layout for Miniaturization
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Solution Overview
Problem
Conventional semiconductor modules with vertically stacked semiconductor dies face challenges in miniaturization due to the increased length and mounting height required for numerous connection terminals, making them difficult to integrate into thin electronic devices like cellular phones.
Innovation Solution
A semiconductor module design featuring a circuit substrate with non-overlapping data input/output pads and control/address pads on separate peripheral portions of vertically stacked dies, allowing for reduced substrate area and mounting height, and improved electrical connectivity through wire bonding and redistributing lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple connection terminals are formed on the circuit substrate to connect vertically stacked semiconductor dies, then electrical connectivity between dies is improved, but the substrate area and module length increase
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of connection terminals to a three-dimensional vertical stacking configuration. Multiple semiconductor dies are stacked vertically with connection terminals formed on different vertical levels, allowing electrical connectivity between dies without increasing substrate area. This dimensional transition enables high-density interconnection while maintaining a compact footprint.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor dies are stacked vertically, with each die containing functional circuits and connection terminals. The dies are nested in the vertical dimension, with lower dies supporting upper dies, and connection terminals on each die connecting to corresponding terminals on adjacent dies. This nesting approach maximizes electrical connectivity while minimizing the horizontal substrate area required.
2Reliability
If numerous connection terminals are arranged on the circuit substrate, then signal transmission between dies is enabled, but the mounting height increases
Solution Approach 1:
The patent redistributes connection terminals across multiple vertical levels by stacking semiconductor dies. Instead of arranging all connection terminals in a single plane which increases mounting height, the terminals are distributed across different heights corresponding to different die levels. This vertical distribution enables signal transmission between dies while controlling the overall mounting height of the module.
3Ease of manufacture
If connection terminals are formed on the peripheral portion of the circuit substrate, then ease of wire bonding is improved, but the available substrate area for other functions is reduced
Solution Approach 1:
The patent segments the substrate area into distinct functional zones: peripheral regions dedicated to connection terminals for wire bonding access, and central regions for active circuit elements. This segmentation allows connection terminals to be positioned at the periphery where wire bonding is most accessible, while preserving the central substrate area for高密度 circuit integration. The peripheral positioning of terminals on stacked dies provides multiple access points for wire bonding without compromising the active area of each die.
Data Source
AI summary
A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.