Stacked Semiconductor Package Molding with Tape Masking

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing stacked semiconductor package structures face limitations in the size and type of packages, number of electrical I/O, and suffer from contamination and increased costs due to reflow processes and encapsulant flashing, which affect product yield and reliability.

Innovation Solution

A method involving mounting semiconductor chips on a substrate with supporting members, using bonding wires for electrical connection, and a molding process with a tape on the second substrate to expose solder pads, eliminating the need for reflow and special molds, thus preventing contamination and cost increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a reflow process is performed to electrically connect the second BGA substrate to the first BGA substrate through solder balls, then electrical connection between substrates is achieved, but contamination of the semiconductor chip and first BGA substrate occurs, reducing product yield and reliability

Engineering Contradiction:

Improveproduct yieldVSAvoidcontamination

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and removes the harmful reflow process from the manufacturing sequence. Instead of using reflow to connect the second substrate, the invention uses a molding process that encapsulates the structure while exposing the necessary pads, thereby eliminating the contamination source while achieving electrical connection through alternative means

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent converts the potential harm of encapsulant flashing into a benefit by using the molding process to simultaneously encapsulate and expose the necessary pads. The encapsulant that would normally cause contamination is instead used to protect the structure while the exposed pads enable electrical connection without reflow

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Length of stationary object

If the encapsulant height is minimized to below 0.3 mm to meet solder ball height limitations, then stacking process limitations are satisfied, but the difficulty of the process increases

Engineering Contradiction:

Improveencapsulant heightVSAvoidprocess difficulty

Core Design Contradiction:

Length of stationary objectVSEase of manufacture

Solution Approach 1:

Instead of minimizing encapsulant height to accommodate solder balls, the patent inverts the approach by using a molding process that can accommodate various encapsulant heights while exposing the necessary pads. The process is designed around the molding capability rather than constraining the molding to meet solder ball limitations

Inventive Principle:

Principle #13The other way round (Inversion)

3Reliability

If a special mold with protruding portion is used to prevent bonding wires from touching the mold, then wire contamination is prevented, but process cost increases

Engineering Contradiction:

Improvewire contamination preventionVSAvoidprocess cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent extracts and eliminates the need for special mold features by changing the process sequence. Instead of using a special mold to prevent wire contamination, the invention performs wire bonding before molding, allowing the use of a conventional mold and eliminating the need for costly mold modifications

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for flexible package stacking, reduced contamination, and lower fabrication costs by avoiding reflow processes and encapsulant flashing, while ensuring reliable electrical connections.

Implementation Method 1

connecting electrically the first and second substrates through bonding wires

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

performing a molding process to form on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires and the tape

Methodology Applied

Scientific EffectPhase change: Phase Change

Data Source

PatentUS8183092B2Method of fabricating stacked semiconductor structure

Publication Date: 2012.05.22 SILICONWARE PRECISION IND CO LTD

AI summary

A stacked semiconductor structure and fabrication method thereof are provided. The method includes mounting and connecting electrically a semiconductor chip to a first substrate, mounting on the first substrate a plurality of supporting members corresponding in position to a periphery of the semiconductor chip, mounting a second substrate having a first surface partially covered with a tape and a second surface opposite to the first surface on the supporting members via the second surface, connecting electrically the first and second substrates by bonding wires, forming on the first substrate an encapsulant for encapsulating the semiconductor chip, the supporting members, the second substrate, the bonding wires, and the tape with an exposed top surface, and removing the tape to expose the first surface of the second substrate and allow an electronic component to be mounted thereon. The present invention prevents reflow-induced contamination, spares a special mold, and eliminates flash.