Stacked Semiconductor Device With Distinct MTJ Critical Current Densities
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Solution Overview
Problem
Contemporary semiconductor devices with integrated memory and logic elements face limitations in speed and power consumption, particularly with flash memory devices, necessitating the development of faster and more energy-efficient non-volatile memory solutions.
Innovation Solution
A semiconductor device comprising a chip stack with distinct magnetic tunnel junctions on each chip, where the first chip has a high critical current density for magnetization reversal, enhancing retention characteristics, and the second chip has a lower critical current density for faster switching, allowing for both non-volatile memory and random access memory cells with improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory devices are used for non-volatile storage, then data retention is improved, but operating speed deteriorates
Solution Approach 1:
The patent divides the memory system into two separate chips: a first chip containing magnetic tunnel junctions with high critical current density for non-volatile storage, and a second chip containing magnetic tunnel junctions with low critical current density for high-speed access. This segmentation allows each chip to be optimized for its specific function, resolving the contradiction between data retention and operating speed.
Solution Approach 2:
The patent applies local quality by giving different critical current density characteristics to different regions (chips) of the memory system. The first chip has high critical current density for stability and retention, while the second chip has low critical current density for fast switching, allowing each local region to have the properties needed for its specific purpose.
2Reliability
If magnetic tunnel junctions with high critical current density are used, then retention characteristics are improved, but power consumption increases
Solution Approach 1:
The patent segments the memory system into two chips with different critical current density characteristics. The first chip uses high critical current density MTJs for non-volatile storage where retention is paramount, while the second chip uses low critical current density MTJs for applications where power consumption and switching speed are more critical, thus resolving the energy-retention contradiction.
Solution Approach 2:
The patent changes the critical current density parameter of the magnetic tunnel junctions between the two chips. By adjusting this key parameter, the first chip achieves high retention characteristics while the second chip achieves low power consumption, allowing the system to optimize for different operational requirements.
3Speed
If magnetic tunnel junctions with low critical current density are used, then switching speed is improved, but retention characteristics deteriorate
Solution Approach 1:
The patent segments the memory system into two specialized chips: the first chip with high critical current density MTJs optimized for retention, and the second chip with low critical current density MTJs optimized for switching speed. This segmentation allows each chip to excel at its specific function without compromise.
Solution Approach 2:
The patent applies local quality by giving different critical current density characteristics to different chips based on their specific functional requirements. The second chip has low critical current density for fast switching operations, while the first chip has high critical current density for stable data retention, allowing each local region to have the properties needed for its specific purpose.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides semiconductor devices with enhanced retention characteristics for non-volatile memory and high-speed, low-power consumption random access memory, addressing the limitations of existing technologies by optimizing the critical current densities of magnetic tunnel junctions in a stacked chip configuration.
Implementation Method 1
A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction
Data Source
AI summary
A semiconductor device comprises a first semiconductor chip comprising a first substrate. A first magnetic tunnel junction is on the first substrate. A second semiconductor chip comprises a second substrate. A second magnetic tunnel junction is on the second substrate. The second semiconductor chip is positioned on the first semiconductor chip to form a chip stack. A first critical current density required for magnetization reversal of the first magnetic tunnel junction is different than a second critical current density required for magnetization reversal of the second magnetic tunnel junction.