Stacked Semiconductor Package With Integrated Decoupling Capacitor
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Solution Overview
Problem
The existing package on package (PoP) semiconductor assembly faces challenges in enhancing the performance of the system-on-chip (SOC) package due to increased input/output connections and height limitations between stacked packages, making it difficult to design additional electronic devices effectively.
Innovation Solution
A semiconductor package assembly is designed with a stacked configuration of a SOC package and a memory package, where the memory package includes a decoupling capacitor and is bonded to a base with conductive structures connecting to the SOC package, allowing for enhanced power delivery and noise mitigation without increasing package dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional electronic devices are designed to enhance SOC package performance, then performance is improved, but package height increases beyond limitations
Solution Approach 1:
The patent transitions from horizontal placement to vertical stacking, arranging the SOC package, memory package, and decoupling capacitor in a vertical column configuration. This dimensional change allows multiple components to coexist within the same footprint area, improving performance without increasing the horizontal package dimensions beyond limitations.
2Power
If decoupling capacitor is integrated on the same package, then power delivery is enhanced, but available area for capacitor placement is insufficient
Solution Approach 1:
The decoupling capacitor is placed in a vertical stack configuration rather than occupying horizontal plane area. The capacitor is positioned above or below the SOC package in the vertical dimension, enabling power delivery enhancement without consuming valuable lateral placement area on the package.
Solution Approach 2:
The decoupling capacitor is integrated into the vertical stack of packages, nesting multiple functional components (SOC package, memory package, decoupling capacitor) within each other's vertical space. This nested arrangement allows the capacitor to be part of the overall package assembly without requiring separate horizontal area.
3Adaptability or versatility
If more input/output connections are added to bottom SOC package, then functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The system is segmented into separate functional packages (SOC package, memory package) that can be manufactured independently with their respective connection requirements. This segmentation allows each package to be optimized separately, managing manufacturing complexity while maintaining overall functionality through vertical integration.
Data Source
AI summary
A semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.