3D Stacked Semiconductor Package with Nested Encapsulation
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Solution Overview
Problem
Conventional semiconductor packaging techniques struggle to create thin, high-speed packages that meet the demands of compact, multi-functional mobile devices due to difficulties in achieving both thinness and high capacity.
Innovation Solution
A semiconductor package design featuring a substrate with stacked semiconductor chips, where a first encapsulant covers a first semiconductor chip and a second encapsulant covers a stack of larger, vertically aligned chips, with conductive connections ensuring efficient electrical connectivity and minimal thickness, allowing for high-speed operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional multi-chip packaging techniques are used, then chip stacking is achieved, but the package thickness cannot be minimized sufficiently
Solution Approach 1:
The patent transitions from planar chip arrangement to vertical stacking configuration, utilizing the third dimension (height) to increase chip capacity while maintaining reduced package thickness. Multiple chips are stacked vertically with conductive connections extending between them, transforming the packaging architecture from 2D to 3D space utilization.
Solution Approach 2:
The patent implements nested encapsulation where a first encapsulant covers individual chips and conductive connections, and a second encapsulant covers the entire stack of chips. This nested structure protects internal components while maintaining compact dimensions, allowing multiple chips to be integrated vertically without proportionally increasing package thickness.
2Quantity of substance
If chip stacking is implemented, then capacity is increased, but high-speed operation becomes difficult to achieve
Solution Approach 1:
The patent divides the electrical connection path into multiple independent conductive connections, each extending directly between specific chips. This segmentation allows for optimized signal routing where each connection can be designed for minimal length and impedance, enabling high-speed operation despite the stacked configuration. The conductive connections are arranged to minimize total path length while maintaining direct electrical contact between chips.
3Stability of the object's composition
If multiple encapsulants are used to cover stacked chips, then structural integrity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies the first encapsulant to cover individual chips and their conductive connections before stacking the chips vertically. This preliminary encapsulation protects the connections and chips during the stacking process, simplifying the overall manufacturing sequence. Subsequently, the second encapsulant is applied to cover the entire stack, creating a robust protective structure without requiring complex simultaneous multi-step encapsulation processes.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip mounted to a substrate, a first encapsulant covering the first semiconductor chip and have first to fourth sidewall surfaces, and a chip stack mounted to the substrate and disposed on the first encapsulant. The chip stack includes a plurality of second semiconductor chips. A second encapsulant covers the chip stack. The second encapsulant may cover the first sidewall surface of the first encapsulant and expose the third sidewall surface of the first encapsulant.