Stacked Semiconductor Package Terminals for Compact Board Layout
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Solution Overview
Problem
Conventional semiconductor packaging processes result in inefficient chip mounting due to large board sizes required to prevent electrical shorts between single-layered external terminals, leading to reduced packaging efficiency and increased size.
Innovation Solution
A semiconductor package with a stacked structure of external terminals, where the second terminal is positioned higher than the first, with a protrusion in the insulation layer to prevent electrical shorts, allowing for smaller board sizes by alternating pad arrangements around slots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layered structure of external terminals is used, then the manufacturing process is simple, but the package size becomes large to prevent electrical shorts
Solution Approach 1:
The patent transitions from a single-layered terminal structure to a multi-layered stacked structure, adding the vertical dimension (Z-axis) to the terminal arrangement. External terminals are positioned at different heights on different layers, connected through conductive patterns and insulation layers, thereby reducing the horizontal area required while maintaining electrical isolation.
Solution Approach 2:
The patent implements a nested structure where multiple terminal layers are stacked vertically, with each layer containing external terminals and conductive patterns. The insulation layers are nested between conductive layers, creating a compact multi-layered configuration that reduces the overall package footprint while preventing electrical shorts between adjacent terminals.
2Reliability
If pads are arranged around slots to prevent electrical shorts, then electrical isolation is improved, but the board size increases
Solution Approach 1:
The patent moves electrical isolation from the horizontal plane to the vertical dimension by stacking terminals on different layers separated by insulation layers. This allows pads to be arranged more compactly on the board without requiring excessive spacing, as electrical isolation is achieved through the layered structure rather than horizontal separation.
Solution Approach 2:
The patent segments the terminal structure into multiple independent layers, each with its own external terminals and conductive patterns separated by insulation layers. This segmentation allows for compact board layout while maintaining electrical isolation between terminals through the layered architecture rather than requiring large horizontal spacing.
3Manufacturing precision
If conventional individual chip packaging is performed, then each chip can be mounted precisely, but the packaging efficiency is low
Solution Approach 1:
The patent merges multiple individual chip packaging operations into a single wafer-level packaging process. Multiple semiconductor chips are packaged simultaneously on a wafer substrate with multiple external terminals and conductive patterns formed in one manufacturing cycle, thereby maintaining precision while dramatically improving packaging efficiency and productivity.
Solution Approach 2:
The patent creates a universal wafer-level package structure that can accommodate multiple different semiconductor chips with various pad configurations. The multi-layered terminal structure and conductive patterns provide a flexible platform that serves multiple packaging functions simultaneously, enabling both precise mounting and high-efficiency production.
Data Source
AI summary
A semiconductor package includes a semiconductor chip having first and second pads, a first insulation layer pattern formed on the semiconductor chip and having first and second openings that expose the first and the second pads, respectively, a first conductive layer pattern elongated along the first insulation layer pattern from the first pad, a first external terminal formed on the first conductive layer pattern, a second insulation layer pattern formed on the first conductive layer pattern and the first insulation layer pattern to expose the first external terminal and having a third opening in communication with the second opening, a second conductive layer pattern elongated along the second insulation layer pattern from the second pad, and a second external terminal formed on the second conductive layer pattern.