3D Stacked Semiconductor Package With Through-Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing the footprint of electronic components while maintaining integration density, as traditional packaging methods are inefficient in stacking and connecting multiple integrated circuit dies effectively.
Innovation Solution
The proposed solution involves a system-in-package (SiP) and three-dimensional integrated circuit (3DIC) packaging technique, where multiple integrated circuit dies are stacked and connected using conductive features and vias within a molding material, forming interconnect structures to enable efficient electrical connections and compact packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional packaging methods are used to package multiple integrated circuit dies, then the packaging process is simpler, but the footprint (form factor) of the packages is larger
Solution Approach 1:
The patent transitions from traditional two-dimensional planar packaging to three-dimensional stacked packaging. Multiple integrated circuit dies are arranged in vertical stacks and connected through vias and conductive structures, enabling significant reduction in package footprint while accommodating complex interconnections between dies in different layers
Solution Approach 2:
The patent implements a nested structure where multiple integrated circuit dies are stacked vertically within a single package footprint. Each die is positioned above another, forming a tower-like configuration that maximizes space utilization and reduces the overall package area required
2Quantity of substance
If multiple integrated circuit dies are stacked and connected using conductive features and vias, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary actions by forming through-vias and conductive structures in the molding compound before or during the die stacking process. This allows for pre-established electrical pathways that simplify subsequent die attachment and interconnection, reducing overall manufacturing complexity despite the three-dimensional architecture
Solution Approach 2:
The molding compound serves multiple functions: it provides mechanical support for stacked dies, establishes electrical connections through integrated through-vias, provides environmental protection, and enables thermal management. This multi-functionality reduces the need for separate components and simplifies the overall manufacturing process
3Volume of stationary object
If three-dimensional integrated circuit packaging is implemented, then package size is reduced, but connection reliability between stacked dies becomes more critical
Solution Approach 1:
The patent uses composite material structures including conductive-filled molding compounds where non-conductive molding material provides mechanical support and protection while conductive particles or structures embedded within provide electrical pathways. This composite approach ensures both structural integrity and reliable electrical connections between stacked dies
Solution Approach 2:
The patent employs rounded via structures and curved conductive pathways within the molding compound, which provide more reliable electrical connections compared to sharp corners. The curved geometries reduce stress concentration and improve current distribution, enhancing connection reliability in the three-dimensional stacked configuration
Data Source
AI summary
Devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first interconnect structure, a first integrated circuit die coupled to the first interconnect structure, and a second integrated circuit die disposed over and coupled to the first integrated circuit die. A second interconnect structure is disposed over the second integrated circuit die. First through-vias are coupled between the first interconnect structure and the second interconnect structure, and second through-vias are coupled between the first integrated circuit die and the second interconnect structure. A molding material is disposed around the first integrated circuit die, the second integrated circuit die, the plurality of first through-vias, and the plurality of second through-vias.