Stacked Semiconductor Device Parasitic Capacitance Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration density, excellent electrical characteristics, reliable frequency performance, long data retention, high-speed data writing, low power consumption, and design flexibility, particularly in reducing size and using flexible substrates.
Innovation Solution
A semiconductor device structure comprising multiple semiconductor and insulating layers with specific metal elements like aluminum and hafnium, and conductive layers, optimized with insulating layers to reduce parasitic capacitance and enhance electrical properties, allowing for a flexible substrate implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor layers and insulating layers are stacked to increase integration density, then the device size is reduced and integration density is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The semiconductor device is divided into multiple functional layers including first and second semiconductor layers, first through fourth insulating layers, and first and second conductive layers. Each layer serves a specific function in the transistor structure, allowing complex functionality to be achieved through systematic segmentation of the device into manageable layers that can be manufactured and analyzed independently
Solution Approach 2:
The patent transitions from planar transistor structures to vertically stacked three-dimensional architecture. Multiple semiconductor and insulating layers are stacked in the vertical dimension to achieve high integration density without proportionally increasing the horizontal device footprint, effectively utilizing the third dimension for device miniaturization
2Reliability
If insulating layers with specific metal elements are used to reduce parasitic capacitance, then electrical characteristics are improved, but the manufacturing precision requirements increase
Solution Approach 1:
The insulating layers are doped with specific metal elements (aluminum and hafnium) at controlled concentrations to create regions with optimized electrical properties. This local quality enhancement reduces parasitic capacitance between conductive layers while maintaining appropriate insulation properties, allowing precise control of electrical characteristics through compositional grading
Solution Approach 2:
The insulating layers are formed as composite materials combining base insulating material with dispersed metal elements (aluminum and hafnium). This composite structure provides both the insulation function and the parasitic capacitance reduction effect, achieving multiple functions through material composition rather than separate components
3Adaptability or versatility
If the semiconductor device is designed for flexible substrate implementation, then adaptability and design flexibility are improved, but the structural stability and reliability may be compromised
Solution Approach 1:
The semiconductor device is constructed with thin-film layers that can be deposited on flexible substrates. The multi-layer structure including semiconductor layers, insulating layers, and conductive layers is designed to maintain structural integrity while accommodating the flexibility of the underlying substrate, enabling bendable and wearable electronic applications
Data Source
AI summary
A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, and a second conductive layer. The second semiconductor layer is positioned over the first semiconductor layer, the second conductive layer is positioned on the second semiconductor layer, and the second insulating layer is provided so as to cover a top surface and a side surface of the second conductive layer. The second conductive layer and the second insulating layer include a first opening, and the third semiconductor layer is provided in contact with a top surface of the second insulating layer, a side surface of the first opening, and the second semiconductor layer. The first insulating layer is positioned between the first conductive layer and the third semiconductor layer, the third insulating layer is positioned between the first insulating layer and the first conductive layer, and the fourth insulating layer is provided so as to surround the first conductive layer.