Stacked Semiconductor Device Serial Opening Formation
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Solution Overview
Problem
Conventional stacked semiconductor devices face challenges in forming serial openings that expose the surface of impurity regions, leading to high electrical resistance and leakage currents, which affect the electrical reliability of the devices.
Innovation Solution
A method involving the formation of seed layers with impurity regions, followed by selective epitaxial growth processes to create plugs and channel layers, and subsequent etching to expose the impurity regions for metal wiring connection, using single crystalline silicon and silicon germanium materials, with etching stop layers and selectivity to control the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the serial opening is formed to expose only the plug on the semiconductor substrate, then the manufacturing process is simpler, but the electrical resistance of the metal wiring increases
Solution Approach 1:
The patent applies preliminary action by forming an etching stop layer (silicon germanium layer) before the final etching step. This stop layer is deposited in advance to control the etching depth and ensure the serial opening exposes the semiconductor substrate surface rather than stopping at the plug interface, thereby preventing high electrical resistance while maintaining manufacturing feasibility.
2Reliability
If the serial opening exposes the surface of the semiconductor substrate, then the electrical resistance decreases, but leakage current through the semiconductor substrate increases
Solution Approach 1:
The patent uses an etching stop layer (silicon germanium layer) as an intermediary structure. This layer is positioned between the plug and the semiconductor substrate, allowing the serial opening to expose the substrate surface for low resistance connection while the stop layer itself prevents direct exposure that would cause leakage current, thus mediating between the two conflicting requirements.
Solution Approach 2:
The patent changes the material parameter by using silicon germanium for the etching stop layer, which has different etching characteristics compared to silicon. This material parameter change allows selective etching to stop at the desired depth, exposing the substrate surface without creating conditions for leakage current.
3Ease of manufacture
If conventional etching time control is used to form the serial opening, then the process is simpler, but the precision of exposing the semiconductor substrate surface deteriorates
Solution Approach 1:
The etching stop layer serves as an intermediary reference layer that provides a clear etching endpoint. Instead of relying on time-based control, the etching process stops when it reaches this distinct intermediate layer, providing precise control over the exposure depth of the semiconductor substrate surface while maintaining a relatively simple etching process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the accurate exposure of impurity regions, reducing electrical resistance and improving the electrical reliability of stacked semiconductor devices by enabling direct contact between metal wiring and the semiconductor substrate.
Implementation Method 1
a first SEG process may be carried out on the exposed surface of the seed layer to form one or more first plugs A second SEG process may be performed on the one or more first plugs to form one or more second plugs A third SEG process may be carried out on the first insulation interlayer pattern to form a first channel layer
Data Source
AI summary
In a method of manufacturing a stacked semiconductor device, a seed layer including impurity regions may be prepared. A first insulation interlayer pattern having a first opening may be formed on the seed layer. A first SEG process may be carried out to form a first plug partially filling the first opening. A second SEG process may be performed to form a second plug filling the first opening. A third SEG process may be carried out to form a first channel layer on the first insulation interlayer pattern. A second insulation interlayer may be formed on the first channel layer. The second insulation interlayer, the first channel layer and the second plug arranged on the first plug may be removed to expose the first plug. The first plug may be removed to form a serial opening. The serial opening may be filled with a metal wiring.