Stacked Semiconductor Package Using Side Surface Connection Patterns
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing stacked semiconductor packages require the formation of through-electrodes or conductive wires for electrical connection, which complicates the manufacturing process, increases package volume, and risks damaging the semiconductor chips.
Innovation Solution
A stacked semiconductor package design that electrically connects semiconductor chips using connection patterns formed on the outer surfaces, eliminating the need for through-electrodes or conductive wires, and includes a method of stacking semiconductor chips in a staggered step-like configuration with inclined surfaces and pads for direct electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive wires are used to electrically connect stacked semiconductor chips, then electrical connectivity is achieved, but the package volume increases due to the need for spacers to prevent short-circuits
Solution Approach 1:
The patent transitions from using conductive wires extending vertically between chips to forming connection patterns directly on the side surfaces of the chips. This dimensional change allows electrical connection without requiring additional vertical space for spacers, thereby reducing package volume while maintaining connectivity.
Solution Approach 2:
The invention extracts and eliminates the spacer component from the packaging structure by directly forming connection patterns on the chip side surfaces. This removal of the spacer element directly reduces the overall package volume while achieving the same electrical connection function.
2Reliability
If through-electrodes are formed in semiconductor chips for electrical connection, then electrical connectivity is achieved, but the manufacturing process becomes complicated and chips are likely to be damaged
Solution Approach 1:
The patent extracts and eliminates the through-electrode structure from the chip design. Instead of forming holes through the entire chip thickness, connection patterns are formed only on the side surfaces, removing the complex drilling, plating, and alignment processes associated with through-electrodes.
Solution Approach 2:
The connection patterns are formed on the chip side surfaces before stacking, allowing for simpler manufacturing processes. This preliminary formation of connection structures avoids the need for complex post-stack through-hole drilling and electrode formation.
3Reliability
If through-holes are defined and through-electrodes are formed in semiconductor chips, then electrical connection is achieved, but the semiconductor chips are likely to be damaged during the process
Solution Approach 1:
The invention removes the through-hole drilling and through-electrode formation processes that pose damage risks to chips. By forming connection patterns only on the side surfaces, the patent eliminates the mechanical stress, heat, and alignment errors associated with drilling through the entire chip thickness.
Data Source
AI summary
A stacked semiconductor package and a method for manufacturing the same. The stacked semiconductor package includes a semiconductor chip module having two or more semiconductor chips which are stacked in the shape of steps. Each of the semiconductor chips includes pads located on an upper surface thereof and an inclined side surface connected with the upper surface. Connection patterns are formed in the shape of lines on the inclined side surfaces and the upper surfaces of the semiconductor chips to electrically connect pads of the semiconductor chips.