Stacked Semiconductor Device Solder Joint Reliability

The patent applies local quality by creating openings with different areas at different locations on the solder resist. Specifically, openings positioned away from the center of the printed wiring board have larger areas, while the central opening has a smaller area. This non-uniform opening area distribution locally adjusts the stress concentration characteristics at each opening, preventing uniform stress distribution and reducing crack formation at critical solder joints.

The patent changes the geometric parameter of the openings (specifically the area) to control stress distribution. By varying the opening area as a parameter based on position, the design optimizes the mechanical stress distribution across the solder joints during thermal cycling, thereby improving reliability while maintaining functional integration.

The patent addresses the vulnerability of fine-pitch solder joints by implementing local quality through position-dependent opening areas. openings for finer wirings and smaller vias are designed with larger areas compared to central openings, providing enhanced mechanical support and stress distribution for these more vulnerable connections, thereby maintaining reliability despite increased circuit density.

The patent applies beforehand cushioning by designing larger openings in advance for solder joints that will experience higher thermal stress. This preventive design approach creates a cushioning effect where the enlarged openings provide additional mechanical support and stress relief before thermal cycling begins, protecting the vulnerable fine-pitch solder joints from crack formation.