Stacked Semiconductor Device Testing via Dedicated Chips
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Solution Overview
Problem
In three-dimensional stacked semiconductor devices, defects in through silicon via (TSV) or wire bonding connections between chips make it difficult to accurately identify and diagnose connectivity issues during testing, as defects in these connections can lead to incorrect identification of defective chips.
Innovation Solution
A semiconductor device and memory module configuration that includes a controller generating pattern signals to test parity bits across chips, storing test results, and outputting error detection signals through a test pad when errors are detected, allowing for accurate identification of connectivity issues between stacked chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of chips is stacked to improve integration degree, then the degree of integration is improved, but defects in TSV or wire bonding connections become difficult to identify and diagnose
Solution Approach 1:
The patent divides the testing function into separate dedicated testing chips that are distinct from the functional memory chips. Each testing chip is responsible for testing specific connection lines (TSVs or wire bonds) between stacked chips, allowing defects to be localized to specific connection segments rather than requiring analysis of the entire stacked structure.
Solution Approach 2:
The patent introduces dedicated testing chips as intermediary elements between the controller and the functional memory chips. These testing chips contain testing circuits that act as mediators to generate test signals, receive test responses, and determine connectivity status of connection lines, thereby facilitating defect detection without interfering with normal memory operations.
2Device complexity
If conventional testing methods are used without dedicated testing circuits, then device complexity is reduced, but error detection precision and connectivity verification accuracy deteriorate
Solution Approach 1:
The testing functionality is segmented into dedicated testing chips separate from functional memory chips. Each testing chip contains specialized testing circuits for generating test patterns, receiving test responses, and determining connectivity, thereby achieving high measurement precision without requiring complex testing logic in every memory chip.
Solution Approach 2:
The testing chips serve multiple functions: generating test signals, receiving test responses from functional chips, determining connectivity status of connection lines, and reporting test results to the controller. This multi-functionality achieves comprehensive error detection precision while keeping individual chip designs relatively simple.
3Reliability
If parity check circuits are implemented in each chip to check test pattern signals, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The error detection function is segmented and concentrated in dedicated testing chips rather than being distributed across all memory chips. Each testing chip contains parity check circuits that specialize in error detection for specific connection lines, achieving high reliability while keeping individual testing chip designs focused and relatively simple.
Data Source
AI summary
A semiconductor device may include a plurality of chips and a test pad. The plurality of chips may check parity bits of a plurality of pattern signals activated in units of specific bits and store test result signals generated by the checking of the parity bits. The plurality of chips may output an error detection signal when an error is detected from any of the test result signals. The test pad may output the error detection signal received from the plurality of chips to an external part. The plurality of chips may be commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal s output through the test pad.