Stacked Semiconductor TSV Layout for Lower I/O Loading
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Solution Overview
Problem
Conventional semiconductor stacking methods overlook power efficiency and cost-effectiveness, relying heavily on signal redistribution layers and wire-bond resources.
Innovation Solution
Employing through-silicon-vias (TSVs) in stacked semiconductor devices, with staggered I/O circuits and offsetting adjacent devices to reduce I/O loading, enabling point-to-point connections and minimizing capacitive loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional stacking methods using signal redistribution layers and wire-bond resources are employed, then electrical interconnection between devices is achieved, but power efficiency deteriorates and cost increases
Solution Approach 1:
The patent extracts and eliminates the conventional signal redistribution layers and wire-bond resources from the stacking architecture. Instead, through-silicon vias (TSVs) are used to provide direct vertical electrical interconnections between stacked devices, removing the unnecessary intermediate components and reducing overall system complexity while improving power efficiency.
Solution Approach 2:
The patent replaces the mechanical wire-bonding system with a semiconductor-based TSV interconnection system. The wire-bond mechanical attachment is substituted with vertically aligned conductive vias etched through the silicon substrate, providing more efficient electrical pathways and reducing parasitic inductance and resistance associated with traditional wire bonds.
2Ease of manufacture
If conventional stacking arrangements are used, then device assembly is simplified, but power efficiency and cost-effectiveness worsen
Solution Approach 1:
The TSV structure serves multiple functions simultaneously: it provides mechanical support for stacking, establishes electrical interconnections between devices, and enables thermal management pathways. This multi-functionality eliminates the need for separate wire-bonding steps and redistribution layers, simplifying the manufacturing process while improving power efficiency through direct vertical connections.
3Area of moving object
If I/O circuits are densely packed in stacked devices, then device area is reduced, but I/O loading increases and system speed deteriorates
Solution Approach 1:
The patent transitions from planar I/O routing to three-dimensional vertical routing using TSVs. By moving signal paths into the vertical dimension, the design achieves point-to-point connections that reduce capacitive loading and signal interference, thereby improving system speed while maintaining compact device area through the stacked architecture.
4Ease of manufacture
If traditional wire-bond resources are used for interconnection, then manufacturing process is conventional and established, but power consumption increases and cost decreases
Solution Approach 1:
The patent changes the fundamental interconnection parameter from lateral wire-bond paths to vertical TSV paths. This parameter change reduces the length and complexity of electrical pathways, decreasing resistive and capacitive losses that contribute to power consumption. The new approach requires updated manufacturing processes but delivers significant power efficiency improvements.
Data Source
AI summary
A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.