Stacked Semiconductor Structure with Variable Insulator Thickness Ratios

Solution Overview

Problem

The increasing number of word lines in semiconductor devices complicates the etching process, leading to defects that degrade the characteristics of these devices, particularly in forming holes through stacked structures.

Innovation Solution

A semiconductor device with a stacked structure featuring units with different thickness ratios of interlayer insulating layers to gates, including a bowing region in the hole structure to reduce defects and improve integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of word lines is increased to improve integration, then device integration is improved, but the difficulty of the etching process increases and defects occur

Engineering Contradiction:

ImproveintegrationVSAvoidetching process

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by making the interlayer insulating layers have different thicknesses in different regions of the stacked structure. Specifically, the interlayer insulating layers adjacent to the hole have a first thickness, while those not adjacent to the hole have a second thickness greater than the first thickness. This localized variation in thickness optimizes the etching process in the critical region near the hole while maintaining structural integrity elsewhere, thereby improving etching precision without compromising overall integration.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements beforehand cushioning by designing the interlayer insulating layers with greater thickness in regions not adjacent to the hole. This provides a buffer or cushion that prevents defects from propagating during the etching process. The thicker layers act as a protective barrier that compensates for potential etching variations or defects, ensuring that the increased number of word lines does not lead to catastrophic failures in the etching process.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

2Productivity

If the number of word lines is increased to improve integration, then device integration is improved, but defects occur that degrade device characteristics

Engineering Contradiction:

ImproveintegrationVSAvoiddevice characteristics

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by making the interlayer insulating layers have different thicknesses in different regions of the stacked structure. Specifically, the interlayer insulating layers adjacent to the hole have a first thickness, while those not adjacent to the hole have a second thickness greater than the first thickness. This localized variation in thickness optimizes the etching process in the critical region near the hole while maintaining structural integrity elsewhere, thereby improving etching precision without compromising overall integration.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements beforehand cushioning by designing the interlayer insulating layers with greater thickness in regions not adjacent to the hole. This provides a buffer or cushion that prevents defects from propagating during the etching process. The thicker layers act as a protective barrier that compensates for potential etching variations or defects, ensuring that the increased number of word lines does not lead to catastrophic failures in the etching process.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10121798B2Semiconductor device including stacked structure

Publication Date: 2018.11.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a substrate, a stacked structure on the substrate, and a vertical structure in a hole passing through the stacked structure. The stacked structure includes units stacked on top of each other in a direction perpendicular to a top surface of the substrate. The units include first units and second units between the first units. Each of the first units includes a first interlayer insulating layer on a first gate, and each of the second units includes a second interlayer insulating layer on a second gate. A ratio of a thickness of the second interlayer insulating layer with respect to a thickness of the second gate is different from a ratio of a thickness of the first interlayer insulating layer with respect to a thickness of the first gate.