Stacked Semiconductor Die Via Interface Error Correction
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Solution Overview
Problem
Existing 3D semiconductor devices face challenges in improving data transfer rates and reliability through via structures while minimizing the number of via structures to enhance integration and reduce power consumption.
Innovation Solution
Implementing semiconductor devices with digital interface circuits that include CRC and ECC encoders/decoders to manage data transmission and error correction, and optimizing via structure connections to improve communication reliability and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of via structures is increased to improve data transfer rate, then data transfer rate is improved, but device complexity and power consumption increase
Solution Approach 1:
Multiple data transmission circuits share a common FIFO circuit, merging the buffering function into a single shared resource rather than having separate FIFOs for each circuit. This reduces the number of via structures needed while maintaining data transfer capability.
Solution Approach 2:
The common FIFO circuit serves multiple data transmission circuits simultaneously, making it a universal resource that handles data for all circuits. This multi-functionality reduces overall device complexity and via structure requirements.
2Reliability
If error detection and correction codes are added to ensure data reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
CRC and ECC codes act as intermediary mechanisms that detect and correct errors in transmitted data. These codes are processed through dedicated encoder/decoder circuits that mediate between the data transmission circuits and the potential errors, ensuring reliability without requiring fundamental changes to the transmission architecture.
3Productivity
If more via structures are used to connect interface circuits, then data transfer rate is improved, but power consumption increases
Solution Approach 1:
Multiple data transmission circuits share a common FIFO circuit, merging the buffering function into a single shared resource rather than having separate FIFOs for each circuit. This reduces the number of via structures needed while maintaining data transfer capability.
4Device complexity
If the number of via structures is reduced to improve integration, then device complexity is reduced, but data transfer rate decreases
Solution Approach 1:
Multiple data transmission circuits share a common FIFO circuit, merging the buffering function into a single shared resource rather than having separate FIFOs for each circuit. This reduces the number of via structures needed while maintaining data transfer capability.
Solution Approach 2:
The system uses clock signals to periodically control data transmission through the shared FIFO circuit, enabling multiple circuits to share the common resource in a time-multiplexed manner. This periodic control allows efficient data transfer without requiring dedicated via structures for each circuit.
Data Source
AI summary
A semiconductor device includes a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit connected to the first semiconductor die by a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmission data and transmit the data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and the second interface circuit is configured to generate response data indicating whether the data signal is normally received and an error correction code of the response data, and transmit a response signal including the response data and the error correction code to the first interface circuit through at least one via structure among the plurality of via structures.