Stacked Semiconductor Package Warpage Compensation
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Solution Overview
Problem
The challenge is to develop smaller, thinner, and more functional semiconductor packages with higher data storage capacities within a given space, while existing stacked semiconductor packages face limitations due to warpage issues during the reflow soldering process, leading to potential short-circuiting of solder balls.
Innovation Solution
The solution involves creating stacked semiconductor packages with connections of varying heights along the longer sides of the package substrates, which are heat-treated to compensate for warpage, ensuring proper alignment and preventing short-circuiting during the reflow soldering process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked semiconductor packages are manufactured with uniform connection heights, then manufacturing process is simple, but warpage during reflow soldering causes short-circuiting of solder balls
Solution Approach 1:
The patent applies local quality by varying the heights of connections at different locations on the package substrate. Specifically, connections along the longer sides of the rectangular substrate have different heights than connections along the shorter sides, and connections at different positions along the same side also have different heights. This localized variation in connection height compensates for warpage occurring at specific regions during reflow soldering, preventing short-circuiting while maintaining manufacturing feasibility.
Solution Approach 2:
The patent employs asymmetry by creating an asymmetric connection height distribution pattern that matches the asymmetric warpage behavior of the package substrate. The connection heights are deliberately made asymmetric with respect to the substrate geometry, with longer sides having different connection height characteristics than shorter sides. This asymmetric design allows the connections to accommodate the asymmetric deformation that occurs during thermal processing.
2Reliability
If connections have varying heights to compensate for warpage, then short-circuiting is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by pre-establishing the varying connection heights before the reflow soldering process occurs. The connections are formed with different heights during the packaging manufacturing process, anticipating the warpage that will occur during subsequent thermal processing. This preliminary configuration ensures that when warpage occurs during soldering, the connections are already positioned to prevent short-circuiting, thereby improving alignment accuracy without requiring ultra-precise control during the soldering process itself.
3Device complexity
If uniform connections are used, then device structure is simple, but warpage causes misalignment and short-circuits
Solution Approach 1:
The patent applies parameter changes by modifying the height parameter of connections based on their location on the package substrate. Instead of maintaining a uniform connection height, the invention varies the height parameter across different regions of the substrate, creating a gradient or stepped height distribution. This parameter variation allows the connection structure to adapt to thermal deformation during soldering, maintaining functional reliability while accepting increased structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses the warpage issue, allowing for more compact and functional semiconductor packages with improved structural integrity and reduced risk of short-circuiting, enabling efficient data storage and processing capabilities.
Implementation Method 1
heat treating the connection portions to stack the second semiconductor package on the first semiconductor package
Data Source
AI summary
A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.