3D Stacked Sensor Capacitor Layer to Eliminate Wire Bonds
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Solution Overview
Problem
Conventional focal plane array (FPA) modules are hindered by the use of expensive long-lead capacitors and susceptible wire bonds, leading to increased module size and heat load, as well as the need for additional capacitors to compensate for wire bond inductance, which complicates handling and reliability.
Innovation Solution
A three-dimensionally stacked FPA module configuration with a bypass capacitor wafer layer that eliminates the need for discrete capacitors and wire bonding, featuring a vertically stacked structure with commercial off-the-shelf capacitors and adhesive layers for communication between the detector, IC, and capacitor layers, reducing module size and thermal weight.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long-lead capacitors and wire bonds are used in conventional FPA modules, then electrical connection and signal processing are achieved, but module size increases and handling reliability decreases
Solution Approach 1:
The patent merges the capacitor and IC layer into a single integrated capacitor-IC layer structure. The capacitor elements are formed directly on the IC layer using standard semiconductor fabrication processes, eliminating the need for separate discrete capacitors and wire bonds. This integration reduces the number of components and interconnections, thereby improving handling reliability and reducing module complexity.
Solution Approach 2:
The patent transitions from a planar layout with separate capacitors positioned around the IC to a three-dimensional integrated structure where capacitors are formed directly on the IC layer. This vertical integration approach reduces the footprint and eliminates the need for extensive wire bonding, addressing both reliability and complexity issues.
2Ease of manufacture
If discrete capacitors are installed by hand with wire bonds, then electrical connection is achieved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The capacitor elements are formed on the IC layer during the standard semiconductor fabrication process before final assembly. This preliminary formation of capacitors eliminates the need for subsequent manual installation and wire bonding operations, significantly improving manufacturing ease and assembly productivity.
Solution Approach 2:
The IC layer itself serves as the substrate for forming capacitors, eliminating the need for separate capacitor components and installation processes. The structure is self-contained and can be manufactured using standard semiconductor fabrication techniques, improving both ease of manufacture and productivity.
3Reliability
If additional capacitors are installed to compensate for wire bond inductance, then electrical performance is improved, but module size increases and heat load increases
Solution Approach 1:
The capacitor elements are integrated directly on the IC layer, placing them in immediate proximity to the IC circuits they support. This integration minimizes the length of current paths and reduces inductance without requiring additional capacitors, thereby maintaining electrical performance while reducing the number of components and associated heat generation.
Data Source
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AI summary
A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.