Stacked Image Sensor Deep Contact Layout for Higher Conversion Gain

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Solution Overview

Problem

Current stacked CMOS image sensors face limitations in achieving high conversion gain due to the capacitance of the floating diffusion node, which affects the efficiency of charge conversion into voltage.

Innovation Solution

The implementation of a deep contact capacitor connected to the source of the source follower transistor, with a well region surrounding the deep contact, reduces the capacitance of the floating diffusion node, thereby enhancing the conversion gain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a conventional stacked CMOS image sensor structure is used, then the pixel area can be maximized and logic elements can be optimized, but the conversion gain is reduced due to high capacitance of the floating diffusion node

Engineering Contradiction:
Improveconversion gainVSAvoidcapacitance of floating diffusion node
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent introduces a deep contact capacitor extending vertically through multiple substrate layers (first substrate and second substrate) to connect the floating diffusion node to ground. This three-dimensional vertical arrangement reduces the horizontal area occupied by capacitance structures while effectively lowering the floating diffusion node capacitance, thereby increasing conversion gain without sacrificing pixel area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The deep contact capacitor acts as an intermediary element between the floating diffusion node and ground. By introducing this intermediate capacitive structure that extends through the substrate layers, the patent provides a controlled path for charge discharge, reducing the effective capacitance at the floating diffusion node and improving voltage conversion efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the floating diffusion node capacitance is reduced to increase conversion gain, then signal processing performance improves, but the structural complexity increases due to deep contacts through multiple layers

Engineering Contradiction:
Improvesignal processing performanceVSAvoidstructural complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The deep contact structure serves multiple functions simultaneously: it provides electrical connection through insulating layers, forms a capacitor to reduce floating diffusion node capacitance, and establishes a ground reference. By combining these functions into a single structural element, the patent reduces overall device complexity while achieving the desired signal processing performance improvement.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively increases the conversion gain by reducing the capacitance, leading to improved image sensor performance.

Implementation Method 1

Each of the plurality of pixels includes a photodiode

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Implementation Method 2

a deep contact capacitor connected to an output terminal of the transfer transistor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20240038792A1Stacked image sensors
Publication Date: 2024.02.01 SAMSUNG ELECTRONICS CO LTD
  • US20240038792A1 patent drawing
  • US20240038792A1 patent drawing
  • US20240038792A1 patent drawing

AI summary

The stacked image sensor includes a first semiconductor substrate and including a photoelectric conversion region and a floating diffusion area, a first insulating layer under the first semiconductor substrate and including a gate of a transfer transistor, a second semiconductor substrate under the first insulating layer and including first impurities of a first conductivity type, and a second insulating layer under the second semiconductor substrate and including a metal pad of a floating diffusion node and a gate of a source follower transistor, wherein the floating diffusion area and the metal pad of the floating diffusion node are electrically connected through a deep contact that is in the first insulating layer and the second semiconductor substrate. The second semiconductor substrate further includes a well region. At least a portion of deep contact may be in the well region. The well region may surround the deep contact.