3D Stacked SoC SRAM Layout for Smaller Low-Power AR Chips
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Solution Overview
Problem
Traditional System-on-a-Chip (SoC) integrated circuit components are limited by the physical size of on-die Static Random-Access Memory (SRAM), which restricts miniaturization and increases power consumption due to long signal paths, and require separate high-speed local memory subcomponents.
Innovation Solution
A vertically stacked arrangement of a SoC die and SRAM subcomponent with through-silicon vias (TSVs) formed in non-functional areas around the active circuitry, eliminating the need for separate high-speed local memory and reducing parasitic effects and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If on-die SRAM is used in traditional SoC, then integration is achieved, but physical size miniaturization is restricted and power consumption increases due to long signal paths
Solution Approach 1:
The patent transitions from a planar 2D integration approach to a 3D stacked architecture. The SRAM is separated from the SoC and placed in a vertical stack, with TSVs providing vertical interconnects. This dimensional change enables miniaturization of the SoC footprint while maintaining short signal paths through vertical connections, thereby reducing power consumption.
Solution Approach 2:
The integrated circuit is segmented into separate functional components: the SoC die and the SRAM subcomponent. This segmentation allows each component to be optimized independently and connected through TSVs, achieving miniaturization without the power consumption penalty of long on-die signal paths.
2Device complexity
If on-die SRAM is used in traditional SoC, then integration is achieved, but separate high-speed local memory subcomponents are still required
Solution Approach 1:
The patent merges the SoC and SRAM into a single stacked integrated circuit component. The SRAM subcomponent is bonded to the SoC die with TSVs providing interconnects, creating a unified component that eliminates the need for separate high-speed local memory while providing sufficient memory capacity for both on-die SRAM and local memory functions.
3Adaptability or versatility
If TSVs are formed in non-functional areas around the periphery, then design flexibility increases and manufacturing flexibility increases, but parasitic effects must be reduced
Solution Approach 1:
The patent applies different characteristics to different regions of the device. TSVs are strategically placed in non-functional peripheral areas with specific geometric configurations that minimize parasitic inductance and resistance. The TSVs are formed with optimized dimensions and patterns that reduce parasitic effects while maintaining design flexibility.
Data Source
AI summary
Three-dimensional integrated circuit component(s) are described including a System-on-a-Chip (SoC) die and a separate static random-access memory (SRAM) subcomponent in a vertically stacked arrangement. Such stacked SoC/SRAM integrated circuit components may form part of a system to render artificial reality images.