Stacked SPAD Sensor Layout for High-Voltage Distance Readout
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Solution Overview
Problem
Conventional semiconductor devices, such as light reception devices, face challenges in balancing miniaturization and high-voltage handling due to the limitations of three-dimensional transistors like FinFETs, which are prone to damage from high voltages, making it difficult to design circuits that require both miniaturization and high-voltage capabilities in a stacked chip structure.
Innovation Solution
A light reception device and distance measuring device are designed with a stacked chip structure where a three-dimensional transistor, like FinFET, is used for the readout circuit on one semiconductor chip, and a two-dimensional transistor is used for high-voltage circuits, such as the laser driver, in a separate region, allowing for efficient miniaturization and high-voltage handling without compromising the device's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a three-dimensional transistor (FinFET) is used for miniaturization, then the mounting density is improved, but the device becomes weak to high voltages and cannot handle relatively high voltage circuits
Solution Approach 1:
The patent segments the semiconductor chip into multiple regions with different transistor types. Specifically, a first region contains three-dimensional transistors (FinFETs) for miniaturized circuits, while a second region contains two-dimensional transistors for high-voltage circuits. This spatial segmentation allows each transistor type to operate in its optimal voltage range, resolving the contradiction between miniaturization and high-voltage resistance.
Solution Approach 2:
The patent applies local quality by assigning different transistor characteristics to different regions of the chip. The three-dimensional transistors are localized to areas requiring miniaturization and low-voltage operation, while two-dimensional transistors are localized to areas requiring high-voltage handling. This localized differentiation enables the chip to simultaneously achieve high density and high-voltage capability in appropriate locations.
2Area of moving object
If a stacked chip structure is adopted to improve mounting density, then the effective mounting area is improved, but the complexity of integrating different transistor types increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacked chip architecture. Multiple semiconductor chips are stacked vertically, with each chip containing specific transistor types optimized for particular functions. This vertical stacking in the third dimension enables high effective mounting density while allowing independent optimization of each layer, thereby managing integration complexity through modular design.
Data Source
AI summary
A light reception device according to an embodiment of the present disclosure includes a stacked chip structure in which at least two semiconductor chips including a first semiconductor chip and a second semiconductor chip are stacked. On the first semiconductor chip, a pixel array section in which pixels each including a light-receiving element are disposed is formed. On the second semiconductor chip, a readout circuit that reads a signal to be outputted by the pixel is formed with use of a three-dimensional transistor, and a circuit using a two-dimensional transistor is formed in a region around a region where the readout circuit is formed.