Stacked Pass-Gate SRAM Layout for Smaller Cell Area
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Solution Overview
Problem
Current semiconductor integrated circuit manufacturing techniques struggle to reduce the cell area of static random-access memory (SRAM) without fundamental changes to the fabrication processes, which is essential for advancing transistor miniaturization and efficiency.
Innovation Solution
The proposed solution involves stacking pass-gate transistors in SRAM cells, allowing for a more compact layout by sharing transistor cells between adjacent SRAM cells, thereby reducing the overall cell area without altering the existing fabrication processes significantly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are arranged in conventional planar configuration, then fabrication process is simple, but cell area is large
Solution Approach 1:
The patent transitions from conventional planar transistor arrangement to a three-dimensional stacked configuration where pass-gate transistors are vertically stacked above pull-up and pull-down transistors. This vertical stacking in the third dimension reduces the horizontal footprint of each SRAM cell while maintaining all necessary transistor functions, directly resolving the contradiction between reducing cell area and managing device complexity.
Solution Approach 2:
The patent merges multiple transistor functions into a compact stacked structure where pass-gate transistors are positioned above pull-up and pull-down transistors sharing common source/drain regions. This consolidation of transistor cells reduces the overall cell area by eliminating redundant structures and optimizing spatial arrangement without fundamentally changing the fabrication process.
2Area of moving object
If transistor size is reduced, then cell area decreases, but fabrication process complexity increases
Solution Approach 1:
Instead of reducing transistor dimensions in the planar direction which complicates fabrication, the patent reduces cell area by stacking transistors vertically. This approach maintains standard transistor dimensions and fabrication processes while achieving area reduction through three-dimensional arrangement, avoiding the need for advanced manufacturing techniques.
Solution Approach 2:
The stacked transistor structure serves multiple functions within a compact volume: pass-gate transistors for bit line control, pull-up transistors for node regeneration, and pull-down transistors for data storage. This multi-functional integration reduces the number of separate transistor cells needed, decreasing overall cell area without requiring new fabrication capabilities.
Data Source
AI summary
Embodiments of present invention provide a SRAM device. The SRAM device includes a first, a second, and a third SRAM cell each having a first and a second pass-gate (PG) transistor, wherein the second PG transistor of the second SRAM cell and the first PG transistor of the first SRAM cell are stacked in a first PG transistor cell, and the first PG transistor of the third SRAM cell and the second PG transistor of the first SRAM cell are stacked in a second PG transistor cell. The first and second PG transistors of the first SRAM cell may be stacked on top of, or underneath, the second PG transistor of the second SRAM cell and/or the first PG transistor of the third SRAM cell.