Stacked SRAM Transistor Layout for Shared Power Rail Integration
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Solution Overview
Problem
Existing microelectronic devices face challenges in efficiently integrating multiple layers with power supply rails and signal lines, leading to inefficiencies in power distribution and signal transmission.
Innovation Solution
The implementation of a microelectronic device with stacked transistors, where pairs of transistors are vertically stacked and connected to common nets, allowing for independent operation and efficient power distribution through shared power lines, while maintaining signal integrity through separate bitlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple adjacent layers are deposited and structured one after the other, then the microelectronic device can be formed with required circuit components, but the device complexity and layer integration efficiency deteriorate
Solution Approach 1:
The patent transitions from traditional planar layer-by-layer deposition to a three-dimensional stacked transistor architecture. Multiple transistor layers are vertically stacked and interconnected through via structures, enabling parallel processing and reducing the number of sequential fabrication steps required. This dimensional change from 2D to 3D integration directly addresses the contradiction by improving productivity without excessively increasing device complexity.
Solution Approach 2:
The patent implements nested structures where smaller functional units (transistor layers) are stacked within and connected to larger structural frameworks. The via structures act as nesting elements that connect different transistor layers vertically, creating a compact integrated architecture. This nesting approach reduces the overall device footprint and simplifies the integration process compared to traditional adjacent layer deposition.
2Reliability
If power supply rails are provided in layers above the FETs, then power distribution is achieved, but the signal transmission efficiency and power distribution effectiveness deteriorate
Solution Approach 1:
The patent merges the power distribution function directly into the transistor stack structure itself. Power supply rails are integrated within the stacked transistor layers rather than being placed in separate adjacent layers. This merging of power distribution pathways with the transistor architecture improves power distribution effectiveness and signal transmission efficiency while reducing the overall layer structure complexity.
Data Source
AI summary
A processor may form a first power line and a second power line. The processor may form a first memory cell with at least six transistors and a second memory cell with at least six transistors. The first pair of transistors of the first memory cell may be stacked vertically and connected at a common net. The common net may be arranged transverse to the first pair of transistors. The first pair of transistors may be configured to share the first power line. The second pair of transistors of the first memory cell may be stacked vertically and connected at a common net. The common net may be arranged transverse to the second pair of transistors. The second pair of transistors may be configured to share the second power line. The transistors of the first pair of transistors are configured to operate independently from the second pair of transistors.