Stacked Storage Capacitors in TFT Substrates for Low Power Displays
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Solution Overview
Problem
Conventional display devices face limitations in achieving low power consumption while maintaining or increasing the capacitance of storage capacitors, which is crucial for portable and wearable devices that require improved image quality and reduced power consumption.
Innovation Solution
A thin film transistor substrate is designed with a combination of polycrystalline semiconductor and oxide semiconductor materials, where the first TFT includes a polycrystalline semiconductor layer and the second TFT includes an oxide semiconductor layer, both formed on the same substrate, with specific electrode and insulating layer configurations to optimize power consumption and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional display devices use traditional storage capacitor designs, then the device structure is simple, but the capacitance cannot be maintained or increased while achieving low power consumption
Solution Approach 1:
The invention divides the storage capacitor into multiple stacked capacitors (first storage capacitor and second storage capacitor) connected in parallel. Each capacitor has its own electrode and insulating layer structure, allowing the total capacitance to be the sum of individual capacitances. This segmentation enables increased total capacitance while maintaining low power consumption by optimizing each individual capacitor's contribution.
Solution Approach 2:
The invention transitions from a single-plane capacitor structure to a multi-layer stacked structure by adding the vertical dimension. The first and second storage capacitors are stacked at different heights with intermediate insulating layers, effectively utilizing three-dimensional space to increase total capacitance without expanding the horizontal area, thereby reducing power consumption per unit area.
2Reliability
If the capacitance of storage capacitors is increased for better image quality, then image quality improves, but power consumption increases
Solution Approach 1:
By segmenting the total capacitance requirement into multiple smaller capacitors stacked in parallel, each capacitor can be optimized for efficient charge storage. The segmented structure allows better voltage distribution and reduced leakage current across individual capacitors, maintaining high image quality while reducing overall power consumption compared to a single large capacitor.
Solution Approach 2:
The invention uses composite insulating layer structures with different materials (first gate insulating layer, intermediate insulating layer, second gate insulating layer) having different dielectric properties. This composite structure optimizes the electrical characteristics of each capacitor, enabling high capacitance with low power consumption by selecting materials with appropriate dielectric constants and thicknesses for each layer.
3Reliability
If multiple stacked storage capacitors are implemented, then capacitance and image quality improve, but device complexity increases
Solution Approach 1:
The invention merges the formation processes of multiple capacitors into unified manufacturing steps. The first and second gate insulating layers, intermediate insulating layers, and electrode structures are formed using combined deposition and patterning processes that simultaneously create multiple capacitor structures, reducing manufacturing complexity despite the increased structural complexity of the final device.
Solution Approach 2:
The intermediate insulating layer serves multiple functions: it acts as an insulator between the first and second storage capacitors, provides mechanical support for the stacked structure, and facilitates the integration of multiple capacitors in a compact arrangement. This multi-functionality reduces the need for additional specialized layers, simplifying the overall device structure.
Data Source
AI summary
A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode.