Stacked Substrate Interconnect for Front-Side CMOS Image Sensors
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Solution Overview
Problem
Conventional stacked integrated chip structures are not suitable for front-side illuminated CMOS image sensors (FSI-CIS) as they do not allow light to pass through, limiting their integration into multi-dimensional integrated chip structures.
Innovation Solution
A method of forming a multi-dimensional integrated chip with tiers connected in a front-to-back configuration, where a first dielectric structure is bonded to the back-side of a second substrate, and an inter-tier interconnect structure with segments having different sidewall angles is formed to electrically couple metal interconnect layers, allowing FSI-CIS to be integrated as front-side image sensors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional stacked integrated chip structures are used, then electrical interconnection between substrates is achieved, but light cannot pass through to reach image sensing elements
Solution Approach 1:
The interconnect structure is divided into multiple segments with different sidewall angles. The first segment has a first sidewall angle and the second segment has a second sidewall angle different from the first. This segmentation allows light to pass through at oblique angles while maintaining electrical connectivity, resolving the contradiction between electrical interconnection and light transmission.
Solution Approach 2:
The interconnect structure employs asymmetric geometry with segments having different sidewall angles rather than uniform cylindrical shapes. This asymmetry creates pathways that allow light to pass through the interconnect structure at certain angles while maintaining electrical connectivity, thereby resolving the contradiction between electrical interconnection and light blocking.
2Productivity
If FSI-CIS are integrated into multi-dimensional chip structures, then performance is improved and power consumption is reduced, but the structure becomes more complex
Solution Approach 1:
The patent integrates FSI-CIS into a multi-dimensional stacked chip structure, transitioning from planar to three-dimensional architecture. This dimensional change enables improved performance and reduced power consumption while the segmented interconnect structure manages the complexity through standardized modular design.
Data Source
AI summary
The present disclosure relates to an integrated chip structure that includes a first substrate having a first thickness. A first plurality of interconnects are within a first dielectric structure on a front-side of the first substrate. A second substrate has a second thickness less than the first thickness. A second plurality of interconnects are within a second dielectric structure on a front-side of the second substrate. A dielectric bonding structure is between a back-side of the second substrate and the first dielectric structure. A through-substrate via extends through the second substrate and between the first and second plurality of interconnects. The through-substrate via includes a first segment extending through the second substrate and a second segment laterally surrounded by the dielectric bonding structure. The first and second segments respectively have a conductive region and a barrier arranged along sidewalls and a horizontally extending surface of the conductive region.