Stacked TFT 2T Capacitorless Memory Cell for Dense Low-Power SoC Memory
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Solution Overview
Problem
Existing embedded memory technologies face challenges in achieving high density and low power consumption, particularly in system-on-a-chip (SoC) technology, where conventional memory cells are limited by the need for capacitors and complex fabrication processes.
Innovation Solution
The implementation of two-transistor capacitorless memory cells with stacked thin-film transistors (TFTs) that eliminate the need for capacitors, utilizing a write transistor and a read transistor, where at least one transistor is a TFT, allowing for higher density and lower standby power through the use of thin-film semiconductor materials and layer transfer techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory cells with capacitors are used, then data storage capability is achieved, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the capacitor component from the memory cell structure entirely, extracting only the essential transistor elements needed for data storage. This is achieved by using a stacked transistor configuration where the first and second transistors work together to provide storage functionality without requiring a separate capacitor, thereby reducing device complexity while maintaining data storage capability
Solution Approach 2:
The patent combines the storage function into the transistor structure itself by stacking the first transistor over the second transistor. The stacked configuration merges the functions of multiple components into a unified structure where the transistors collectively provide both switching and storage capabilities, eliminating the need for separate capacitor components
2Reliability
If traditional memory cells with capacitors are used, then data storage capability is achieved, but power consumption increases
Solution Approach 1:
The patent removes the capacitor component that is typically responsible for high power consumption in traditional memory cells. By extracting this energy-intensive component and replacing it with a capacitorless stacked transistor structure, the invention significantly reduces power consumption while maintaining data storage capability through the transistor configuration
Solution Approach 2:
The patent changes the fundamental operating parameters of the memory cell by transitioning from a capacitor-based storage mechanism to a transistor-based storage mechanism. This parameter change involves using the electrical characteristics and switching behavior of the stacked transistors to achieve storage functionality, thereby altering the energy consumption profile from high to low
3Quantity of substance
If stacked transistor configuration is used, then density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration, stacking the first transistor vertically over the second transistor. This dimensional change increases memory density by utilizing the vertical space above each transistor, effectively multiplying the storage capacity per unit area while managing manufacturing complexity through systematic fabrication processes
Data Source
AI summary
Described herein are memory cells that include two transistors stacked above one another above a support structure where neither one of the transistors is coupled to a capacitor and where at least one of the two transistors is a thin-film transistor. In such 2T capacitorless memory cells, a first transistor may be referred to a write transistor, and a second transistor may be a read transistor. The first transistor may be a three-terminal device having two S/D terminals and a gate terminal, while the second transistor may be a four-terminal device having two S/D terminals and two gate terminals.