Stacked TFT eDRAM Memory Cell Architecture
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Solution Overview
Problem
The challenge in developing embedded DRAM (eDRAM) technology lies in reducing leakage of selector transistors, achieving high density, and scaling capacitors in advanced technology nodes, where conventional logic transistors face limitations in reducing leakage and embedding capacitors in lower metal layers becomes difficult due to aggressive scaling of pitches.
Innovation Solution
The use of thin-film transistors (TFTs) as selector transistors in eDRAM cells, allowing for lower leakage and enabling a stacked architecture with capacitors in upper metal layers, which reduces the aspect ratio of capacitors and increases memory cell density, while moving peripheral circuits below the memory array to minimize footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional logic transistors are used as selector transistors in eDRAM cells, then fabrication compatibility is improved, but leakage current increases
Solution Approach 1:
The patent changes the material parameters of the selector transistor from conventional logic transistor materials to thin-film transistor materials (such as IGZO - indium gallium zinc oxide). This material substitution fundamentally alters the electrical characteristics, achieving significantly lower leakage current while maintaining compatibility with standard semiconductor fabrication processes through established thin-film deposition techniques.
Solution Approach 2:
The patent employs composite material structures in the TFT-based eDRAM cell, combining thin-film transistor materials with capacitor materials in a stacked configuration. The composite structure integrates the low-leakage properties of TFTs with the charge storage capability of capacitors, creating a hybrid device that overcomes the limitations of conventional logic transistor-based designs.
2Quantity of substance
If capacitors are embedded in lower metal layers to achieve high density, then manufacturing complexity increases due to aggressive scaling of pitches
Solution Approach 1:
The patent transitions from planar embedding of capacitors in lower metal layers to a vertical stacked architecture where capacitors are positioned in upper metal layers. This dimensional change from 2D planar to 3D vertical stacking allows capacitors to be formed in more accessible metal layers with larger pitch dimensions, significantly reducing manufacturing complexity while achieving high memory cell density through vertical space utilization.
3Quantity of substance
If TFTs are used as selector transistors with capacitors in upper metal layers, then memory cell density increases, but footprint of memory arrays decreases
Solution Approach 1:
The patent utilizes vertical stacking to arrange TFTs and capacitors in multiple metal layers (e.g., capacitor in M6, TFT in M7, bitline in M8). This three-dimensional stacking approach packs more memory cells into the same planar footprint by exploiting the vertical dimension, thereby increasing memory cell density while minimizing the overall area occupied by the memory array.
Data Source
AI summary
Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.