Stacked TFT Array Substrate Layout for Leakage-Safe High Integration
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Solution Overview
Problem
The complexity of panel manufacturing for electronic devices, such as display devices, leads to challenges in reducing transistor size while maintaining performance, and existing technologies face issues with leakage current and damage during the fabrication process.
Innovation Solution
A thin film transistor (TFT) array substrate structure is developed where at least two transistors are stacked perpendicular to the substrate, with overlapping gate electrodes connected to corresponding nodes to reduce leakage current and properly disposed contact holes to prevent damage, allowing for reduced transistor area and improved electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are highly integrated to achieve high resolution, then device performance improves, but transistor size cannot be reduced further due to fabrication process limitations
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional stacking, where multiple transistors are arranged vertically along the thickness direction of the substrate. This dimensional change allows higher integration density without further reducing the lateral footprint of individual transistors, thereby maintaining manufacturability while achieving high resolution.
Solution Approach 2:
The patent implements nested transistor structures where transistors are embedded within insulating films and stacked in multiple layers. Each transistor is nested within the substrate thickness, with lower transistors positioned beneath upper transistors, creating a nested configuration that maximizes space utilization without compromising fabrication feasibility.
2Area of stationary object
If multiple transistors are stacked vertically to reduce area, then area occupied by transistors decreases, but leakage current increases due to gate electrode connections
Solution Approach 1:
The patent segments the gate electrodes of stacked transistors into electrically independent sections using insulating films. Each gate electrode is divided into first and second portions separated by insulating layers, preventing electrical connection between stacked transistors and thereby eliminating leakage current while maintaining compact vertical arrangement.
Solution Approach 2:
The patent introduces insulating films as intermediary layers between gate electrodes of adjacent transistors. These insulating films act as mediators that physically separate and electrically isolate the gate electrodes, preventing direct contact and leakage current flow while allowing the transistors to remain in close vertical proximity for area reduction.
3Reliability
If contact holes are formed for electrical connection between stacked transistors, then electrical connectivity is achieved, but elements may be damaged during fabrication
Solution Approach 1:
The patent extracts the need for contact holes by eliminating the requirement for vertical electrical connections between stacked transistors. By using laterally extending source and drain electrodes that make contact with underlying transistor elements without requiring penetrating contact holes, the design removes the harmful fabrication step while maintaining necessary electrical connectivity.
Solution Approach 2:
The patent implements preliminary action by designing source and drain electrodes that extend laterally to contact underlying elements before final assembly. This preliminary lateral contact arrangement eliminates the need for subsequent contact hole formation that could cause damage, as all necessary electrical connections are established through the lateral electrode extensions in earlier fabrication stages.
Data Source
AI summary
Provided are a thin film transistor army substrate and an electronic device including the same. The thin film transistor army substrate includes a first active layer disposed on a substrate, a first gate insulating film disposed on the first active layer, a first gate electrode disposed on the first gate insulating film to overlap a part of the first active layer, a first insulating film disposed on the first gate electrode, a second active layer disposed on the first insulating film to overlap the first active layer and the first gate electrode, a second gate insulating film disposed on the second active layer, and a second gate electrode disposed on the second gate insulating film to overlap a part of the second active layer. The first gate electrode and the second gate electrode overlap each other, and thus it is possible to reduce an area occupied by transistors.