Stacked Transistor Vertical Interconnect for Backside Routing
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Solution Overview
Problem
As semiconductor devices continue to increase in integration density, challenges arise from fabrication and design, particularly in stacked device configurations like CFETs, where reducing minimum feature sizes introduces additional features that affect performance and efficiency.
Innovation Solution
The implementation of a vertical interconnect structure through stacked transistors, which includes a metal interconnect structure and a bottom dielectric structure, reduces capacitance and increases device speed while allowing for backside interconnect routing, eliminating the need for large frontside interconnects and improving process integration and routing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional features are introduced that affect performance and efficiency
Solution Approach 1:
The patent transitions from planar transistor layouts to vertically stacked transistors, utilizing the third dimension (height) to increase integration density. Multiple transistors are stacked one on top of another, allowing more devices to be packed into the same footprint area without proportionally increasing complexity in the lateral dimensions.
Solution Approach 2:
The stacked transistor structure is divided into distinct functional segments including source regions, drain regions, channel regions, and gate structures for each transistor in the stack. This segmentation allows independent optimization of each transistor while maintaining compact vertical integration.
2Adaptability or versatility
If frontside interconnects are enlarged to accommodate routing needs, then routing flexibility improves, but device area increases
Solution Approach 1:
The patent introduces backside interconnects that route signals from the rear of the device, utilizing the vertical dimension and backside surface to provide additional routing paths. This relieves congestion on the frontside without requiring enlargement of frontside interconnect structures.
Solution Approach 2:
The interconnect system is segmented into frontside interconnects and backside interconnects, with each handling specific routing functions. This segmentation allows optimized routing on each surface without compromise to overall routing flexibility while minimizing total area usage.
Data Source
AI summary
In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source/drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source/drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.