Stacked Transistor Contact Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of miniaturizing semiconductor devices is exacerbated by the increase in parasitic capacitance due to the need for contacts that penetrate semiconductor substrates to make electrical connections between transistors on different layers.
Innovation Solution
A semiconductor device design that stacks transistors while minimizing parasitic capacitance by using non-overlapping contacts and insulating layers, with specific configurations for low and high-voltage transistors, and a method of manufacturing that maintains insulating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are provided to penetrate the semiconductor substrate to make electrical connections between transistors on different layers, then electrical connectivity between layers is achieved, but parasitic capacitance increases
Solution Approach 1:
An insulating layer is introduced as an intermediary between the first contact (penetrating the first semiconductor substrate) and the second contact (on the second semiconductor substrate). This insulating layer prevents direct electrical contact while maintaining structural connection, thereby reducing parasitic capacitance between the contacts and the semiconductor substrate while preserving electrical connectivity through the contact structure.
Solution Approach 2:
The electrical connection path is segmented into multiple discrete components: a first contact on the first substrate, an insulating layer, and a second contact on the second substrate. This segmentation allows each component to be optimized independently - the contacts provide electrical connectivity while the insulating layer minimizes parasitic capacitance, resolving the contradiction between connectivity and capacitance reduction.
2Productivity
If multiple semiconductor substrates are stacked to achieve miniaturization, then device density increases, but parasitic capacitance from inter-layer connections increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking of semiconductor substrates. By utilizing the vertical dimension, multiple transistor layers can be integrated within a smaller footprint area, achieving miniaturization and increased device density. The insulating layer between substrates in this stacked configuration minimizes parasitic capacitance, allowing high-density integration without proportionally increasing harmful electrical effects.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first transistor on the semiconductor substrate, an insulating layer above the semiconductor substrate in a first direction, a semiconductor layer provided on the insulating layer and partially overlapping the semiconductor substrate and the insulating layer in the first direction, a second transistor on the semiconductor layer, a first contact penetrating the insulating layer in the first direction such that the first contact is not in contact with the semiconductor layer, a second contact extending parallel to the first contact, and a memory cell array provided above the insulating layer and electrically connected to the second transistor through the second contact.