Stacked Transistor Layout With Separation Layers for Compact Semiconductors
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Solution Overview
Problem
The challenge of reducing the size of semiconductor devices while maintaining transistor density without increasing manufacturing complexity.
Innovation Solution
The semiconductor device incorporates a first semiconductor layer with first transistors, an insulating layer, a second semiconductor layer with second transistors separated by a separation layer, and a peripheral circuit design that includes low and high voltage MOS transistors with optimized layout and separation layers to reduce size and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of the semiconductor device is reduced, then the layout area for transistors is reduced, but the transistor density increases excessively which increases manufacturing difficulty
Solution Approach 1:
The invention divides the transistor structure into multiple segments: first transistors formed in a first semiconductor layer and second transistors formed in a second semiconductor layer. This segmentation allows the device to achieve high integration without excessively increasing the density in a single layer, thereby reducing manufacturing difficulty while maintaining compact size.
Solution Approach 2:
The invention transitions from a two-dimensional layout to a three-dimensional structure by stacking semiconductor layers vertically. Multiple transistors are arranged across different layers (first semiconductor layer and second semiconductor layer), enabling high-density integration without increasing the planar footprint or the density within any single layer, thus avoiding excessive manufacturing complexity.
2Volume of moving object
If the density of transistors is increased to reduce device size, then the layout area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The transistor population is segmented across two separate semiconductor layers. First transistors are formed in the first semiconductor layer and second transistors are formed in the second semiconductor layer, with each layer having its own separation layers. This segmentation distributes the complexity across multiple simpler fabrication steps rather than requiring extreme density in a single layer.
Solution Approach 2:
The invention utilizes the vertical dimension by stacking the first and second semiconductor layers. This three-dimensional arrangement achieves compact device volume without requiring excessive two-dimensional density, thereby reducing manufacturing complexity while maintaining small form factor.
3Reliability
If separation layers are added between transistors, then transistor isolation is improved, but device complexity increases
Solution Approach 1:
Separation layers are segmented and placed strategically between adjacent transistors within each semiconductor layer. The first separation layers are positioned between first transistors in the first semiconductor layer, and second separation layers are positioned between second transistors in the second semiconductor layer. This segmented approach provides effective isolation without requiring a single complex isolation structure throughout the entire device.
Data Source
AI summary
A semiconductor device includes a first semiconductor layer, a plurality of first transistors provided on the first semiconductor layer, an insulating layer provided on the first semiconductor layer and covering the plurality of first transistors, a second semiconductor layer provided in the insulating layer, a plurality of second transistors provided on the second semiconductor layer, and a separation layer that extends through the second semiconductor layer between the plurality of second transistors to separate the plurality of second transistors from each other.