Stacked Transistor Threshold Tuning With Gate-Insulator Dipoles
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Solution Overview
Problem
Conventional methods face challenges in forming lower transistors with different threshold voltages in stacked integrated circuit devices, as upper transistors overlap lower transistors, making it difficult to achieve multiple stacked transistors with varying threshold voltages without complex patterning processes.
Innovation Solution
The approach involves forming gate insulators with different dipole elements or areal densities, allowing lower transistors to have the same thickness and material for their gate work function layers, while upper transistors have varying thicknesses, enabling the formation of transistors with distinct threshold voltages without requiring multiple patterning processes and omitting high-temperature annealing that could damage existing transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional methods are used to form stacked transistors, then area reduction is achieved, but forming lower transistors with different threshold voltages becomes difficult due to upper transistor overlap
Solution Approach 1:
The patent applies preliminary action by forming the gate insulator with dipole elements before forming the gate work function layer. This preliminary configuration of the gate insulator with specific dipole areal densities allows subsequent formation of gate work function layers with uniform thickness to produce transistors with different threshold voltages, avoiding the need for complex patterning processes that would be required if threshold voltage differentiation was attempted after transistor formation.
2Adaptability or versatility
If multiple patterning processes are used to form lower transistors with different threshold voltages, then threshold voltage differentiation is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by varying the dipole areal density at different locations within the gate insulator. Specifically, different regions of the gate insulator contain dipole elements at different areal densities, which creates local differences in threshold voltage. This allows each transistor to have a tailored threshold voltage through spatial variation of dipole concentration, achieving threshold voltage differentiation without complex patterning of the gate work function layer itself.
Solution Approach 2:
The patent applies parameter changes by modifying the dipole areal density parameter within the gate insulator to control transistor threshold voltages. By changing this physical parameter (dipole areal density) rather than changing the gate work function layer thickness or material through multiple patterning steps, the invention achieves threshold voltage differentiation with a single patterning process, significantly reducing manufacturing complexity.
3Manufacturing precision
If high-temperature annealing is used to adjust threshold voltages, then threshold voltage control is improved, but existing transistors may be damaged
Solution Approach 1:
The patent replaces the thermal field (high-temperature annealing) with an electric field mechanism. Instead of using high-temperature thermal processing to adjust threshold voltages, the invention uses dipole elements within the gate insulator that create electric field effects to control threshold voltages. This substitution of the physical mechanism allows precise threshold voltage control without the damaging high-temperature exposure that would compromise transistor integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the creation of integrated circuit devices with transistors having different threshold voltages without complex patterning or high-temperature processes, ensuring uniformity and efficiency in transistor formation.
Implementation Method 1
a first lower gate insulator that includes first dipole elements... a second lower gate insulator that includes second dipole elements... The first dipole elements and the second dipole elements may have different conductivity types, or the first areal density may be different from the second areal density
Data Source
AI summary
Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.