Stacked Transistor Channels With Material-Tuned Threshold Voltages
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining device performance and integration density, particularly in forming stacked transistors with different threshold voltages.
Innovation Solution
The implementation of complementary field-effect transistors (CFETs) with lower and upper nanostructure-FETs, where the channel regions are formed of different semiconductor materials, allowing for distinct threshold voltages and improved device density through vertically stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to improve integration density, then more components can be integrated into a given area, but device performance and manufacturing precision deteriorate
Solution Approach 1:
The patent transitions from planar transistor arrangements to vertically stacked three-dimensional transistors, enabling multiple transistor layers to be integrated within the same footprint area. This dimensional change allows continued scaling of integration density without further reducing minimum feature sizes, thereby maintaining manufacturing precision while increasing component quantity per unit area.
Solution Approach 2:
The invention divides the transistor structure into multiple stacked layers with distinct channel regions formed from different semiconductor materials. Each layer can be independently optimized for specific threshold voltage requirements, allowing simultaneous integration of high-performance and low-power transistors in the same device stack, thus maintaining performance characteristics while achieving higher integration density.
2Adaptability or versatility
If stacked transistors with different threshold voltages are formed using different semiconductor materials, then device performance and adaptability improve, but manufacturing complexity increases
Solution Approach 1:
The patent employs selective epitaxial growth to pre-form alternating layers of different semiconductor materials (e.g., SiGe and Si) with precisely controlled compositions and thicknesses before any transistor fabrication. This preliminary structuring establishes the threshold voltage characteristics in advance, allowing subsequent processing to treat each layer uniformly without requiring complex material-specific steps during transistor formation, thereby reducing manufacturing complexity despite material diversity.
Solution Approach 2:
The invention utilizes controlled variation of semiconductor alloy composition (e.g., Ge content in SiGe) and layer thickness as key parameters to tune threshold voltages across different transistor layers. By adjusting these physical parameters during epitaxial growth, the process achieves diverse electrical characteristics from a single continuous fabrication sequence, avoiding the need for separate processing lines for different transistor types and thus managing manufacturing complexity.
Data Source
AI summary
In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.