Stacked Transistors with Isolation and Common Gate for Lower Capacitance
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Solution Overview
Problem
Three-dimensional transistor structures face challenges such as parasitic capacitance and difficulty in forming inner spacers, with complex and difficult deposition and removal of gate metal processes.
Innovation Solution
A transistor device with a sacrificial layer defining the border between upper and lower transistors, replaced by an isolation region, facilitates controlled formation of inner spacers and gate metal, reducing parasitic capacitance by incorporating an isolation layer within the common gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional transistor structures are used to increase transistor density, then transistor density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts and removes the sacrificial layer from the three-dimensional transistor structure to create an isolation region. This extraction eliminates the harmful parasitic capacitance that would otherwise exist between the upper and lower transistors, while preserving the high-density stacked configuration.
Solution Approach 2:
The patent introduces an isolation region as an intermediary element between the upper and lower transistors. This isolation region acts as a mediator that electrically decouples the two transistor sections, preventing parasitic capacitance formation while allowing the transistors to maintain their vertical stacked arrangement for high density.
2Manufacturing precision
If inner spacers are formed for three-dimensional transistor structures, then device control is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent performs preliminary action by forming the isolation region before creating the inner spacers. This preliminary isolation structure provides a defined border that guides subsequent spacer formation processes, making the manufacturing of inner spacers easier and more precise in the vertical stacked configuration.
3Reliability
If gate metal is deposited and removed for three-dimensional transistor structures, then transistor functionality is achieved, but process complexity increases
Solution Approach 1:
The patent extracts the sacrificial layer that would otherwise complicate gate metal processing. By removing this intermediate layer first, the gate metal deposition and removal processes become simpler and more controllable, while still achieving the required transistor functionality in the three-dimensional structure.
Data Source
AI summary
Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.