Vertically Stacked Transistors for Low-Power In-Memory Neural Computing
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Solution Overview
Problem
Existing neuromorphic processors face challenges in reducing heat generation and power consumption while maintaining efficient in-memory computing capabilities, particularly in implementing synaptic devices for neural networks.
Innovation Solution
A vertically stacked transistor structure is introduced, incorporating a first and second transistor with specific gate insulating layers made of paraelectric and data recording materials, allowing for efficient in-memory computing and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If synaptic devices are implemented in neuromorphic processors for in-memory computing, then computing efficiency is improved, but heat generation and power consumption increase
Solution Approach 1:
The patent transitions from planar 2D transistor layout to vertically stacked 3D transistor structure. By stacking transistors in the vertical dimension, the device achieves higher integration density without proportionally increasing the active area, thereby improving computing efficiency while controlling heat generation per unit area.
Solution Approach 2:
The synaptic device is segmented into multiple functional transistors (first transistor with paraelectric gate insulating layer for computing, second transistor with data recording gate insulating layer for storage) stacked vertically. This segmentation allows independent optimization of computing and storage functions, improving overall efficiency while managing power consumption through selective operation of each segment.
2Productivity
If more synaptic devices are integrated into neuromorphic processors, then neural network capabilities are enhanced, but device area increases
Solution Approach 1:
The patent employs vertical stacking to transition from 2D planar integration to 3D volumetric integration. Multiple transistors are stacked in the vertical direction above a shared substrate area, enabling higher density of synaptic devices without proportionally increasing the chip footprint, thus enhancing neural network capabilities within constrained device area.
Solution Approach 2:
The vertically stacked transistor structure serves multiple functions: the first transistor performs in-memory computing operations with paraelectric material, the second transistor handles data recording with data recording material, and they share common substrate and interconnection structures. This multi-functionality increases effective device density without linearly increasing total device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces heat generation and power consumption while enhancing integration capabilities, enabling more efficient neural network operations.
Implementation Method 1
One of the first gate insulating layer and the second gate insulating layer may include a paraelectric material
Implementation Method 2
The other of the first gate insulating layer and the second gate insulating may include a data recording material
Data Source
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AI summary
A vertically stacked transistor structure may include a first transistor and a second transistor on the first transistor in a first direction. The first transistor may include a first channel, a first source region, a first drain region, a first gate insulating layer, and a first gate electrode. The second transistor may include a second channel, a second source region, a second drain region, a second gate insulating layer, and a second gate electrode. One of the first gate insulating layer and the second gate insulating layer may include a paraelectric material. The other one of the first gate insulating layer and the second gate insulating layer may include a data recording material.