Stacked Vertical FET Contact Formation via Segmented Source Drains
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Solution Overview
Problem
The shrinking topology of vertical field effect transistors (VFETs) poses challenges in forming effective contacts to the source and drain regions, which is critical for maintaining device performance and reducing footprint in semiconductor manufacturing.
Innovation Solution
A method involving epitaxial growth and spacer formation is used to create semiconductor structures with aligned fins, where source and drain regions are formed between lower and upper fins, and dielectric layers are deposited to isolate and connect these regions, allowing for the formation of contacts through selective etching and deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical FET topology is shrunk to reduce device footprint, then device area is reduced, but contact formation to source and drain becomes more difficult
Solution Approach 1:
The source and drain regions are segmented into distinct first and second source drains with separate contact formation processes. The method forms contacts to the first source drain through a first opening and contacts to the second source drain through a second opening, allowing independent optimization of each contact structure despite the shrunk topology.
Solution Approach 2:
The patent utilizes vertical stacking to create multiple source drain regions at different heights (first source drain at lower level, second source drain at upper level). This three-dimensional arrangement allows contact formation from different vertical dimensions, overcoming the limitations of planar shrinkage while maintaining reduced device footprint.
2Reliability
If multiple source drain regions are formed in stacked configuration, then electrical connectivity is improved, but process complexity increases
Solution Approach 1:
The method performs preliminary actions by forming the first source drain, first spacer layer, and first gate stack before forming the second source drain. The first source drain is prepared and isolated in advance, allowing subsequent steps to focus on the second source drain without reworking previous structures. This sequential preparation reduces overall process complexity.
Solution Approach 2:
Different regions of the semiconductor structure are treated with different properties: the first source drain region receives a first dielectric layer for isolation, while the second source drain region receives a second dielectric layer. Each source drain contact region has customized dielectric isolation and contact hole formation parameters optimized for its specific location and function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable electrical contacts to both the upper and lower FETs in a double vertical stacked FET configuration, facilitating efficient electrical connectivity and maintaining performance while reducing device size.
Implementation Method 1
epitaxially growing a first source drain on the semiconductor structure between a first lower fin in a first region of the semiconductor structure and a second lower fin in a second region of the semiconductor structure
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method including epitaxially growing a first source drain on the semiconductor structure between a first lower fin in a first region of the semiconductor structure and a second lower fin in a second region of the semiconductor structure, forming a first spacer layer on the first source drain, where a lower horizontal surface of the first spacer layer is coplanar with an upper horizontal surface of the first source drain, forming a lower gate stack surrounding the first lower fin and surrounding the second lower fin on exposed surfaces of the semiconductor structure, where a lower horizontal surface of the gate stack is coplanar with an upper horizontal surface of the first spacer layer, forming an interlayer dielectric on exposed surfaces of the first spacer layer.