Stacked Conductive Via Capacitor Structure to Minimize Short Circuits

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Solution Overview

Problem

The challenge in achieving high integration density of capacitors is exacerbated by the risk of short circuits between adjacent conductive vias due to high aspect ratios and critical dimensions during the etching process, which are critical for via formation.

Innovation Solution

A capacitor structure with stacked conductive vias, where the lateral surfaces of the vias are discontinuous, reducing the aspect ratio and minimizing the risk of short circuits, and incorporating support layers to facilitate controlled etching and plating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the aspect ratio of conductive vias is increased to achieve high integration density, then the integration density is improved, but the risk of short circuits between adjacent conductive vias increases

Engineering Contradiction:

Improveintegration densityVSAvoidshort circuit risk

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The conductive via structure is segmented into multiple sections with different lateral dimensions. The via includes a top portion with a first lateral dimension and a bottom portion with a second lateral dimension, creating discrete segments that are less prone to shorting while maintaining high density integration

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The conductive via employs asymmetric dimensional characteristics along its height, with the top portion having different lateral dimensions compared to the bottom portion. This asymmetric design allows optimization of each section for its specific function, reducing short circuit risk while achieving high integration density

Inventive Principle:

Principle #4Asymmetry

2Manufacturing precision

If the critical dimension (width of top end) of conductive vias is increased to reduce under etch risk, then the manufacturing reliability is improved, but the risk of short between adjacent conductive vias increases

Engineering Contradiction:

Improveunder etch riskVSAvoidshort circuit risk

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The via structure divides the conductive path into segments with different lateral dimensions, allowing the top portion to have sufficient width for manufacturing control while the lower portions can be narrower, thus preventing shorts while maintaining manufacturing precision

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the conductive via have different lateral dimensions optimized for their specific locations. The top portion has larger dimensions for manufacturing control, while lower portions have reduced dimensions to prevent shorting, applying local quality variations to solve the contradiction

Inventive Principle:

Principle #3Local quality

3Productivity

If the aspect ratio of conductive vias is increased to reduce via width, then the integration density is improved, but the manufacturing control difficulty increases

Engineering Contradiction:

Improveintegration densityVSAvoidprocess control difficulty

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The high aspect ratio via is segmented into multiple portions with different lateral dimensions, making the manufacturing process more controllable by breaking down the single complex via formation into manageable sections that can be processed and controlled more easily

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12581671B2Capacitor structure with two stacked conductive vias

Publication Date: 2026.03.17 NAN YA TECH

AI summary

A capacitor structure and a method of manufacturing a capacitor structure are provided. The capacitor structure includes a conductive via, an intermediate dielectric layer and a top electrode. The conductive via includes a neck portion located near a middle portion thereof. The intermediate dielectric layer is disposed on the conductive via. The top electrode is disposed on the intermediate dielectric layer.