Stacked Via Layout with Keep-Out Zones for Thermal Stress Relief
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Solution Overview
Problem
Stacked via structures in semiconductor integrated circuits experience high tensile stress during thermal cycling, leading to delamination or cracking, which impairs the reliability of the IC chip.
Innovation Solution
Implementing a keep-out-zone (KOZ) in the interconnect structure to avoid forming stacked via structures in high-stress areas and reducing the number of contact vias in these regions, along with adjusting the location and structure of stacked via structures to minimize stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked via structures are formed under UBM features to provide electrical connection, then connectivity is achieved, but high tensile stress causes delamination or cracking during thermal cycling
Solution Approach 1:
The patent extracts the problematic stacked via structures from high-stress regions (under UBM features) and relocates them to low-stress regions. By removing via structures from areas experiencing high tensile stress during thermal cycling, the source of delamination and cracking is eliminated while electrical connectivity is maintained through重新 positioned vias.
Solution Approach 2:
The patent applies local quality by creating different via structure configurations in different regions of the substrate. High-stress regions under UBM features have no stacked vias (keep-out zones), while low-stress regions contain the via structures. This spatial variation in structure quality optimizes reliability by placing vias only where they will not experience damaging stresses.
2Reliability
If stacked via structures are formed to connect UBM feature and IC chip, then electrical connection is established, but delamination or cracking occurs during thermal cycling
Solution Approach 1:
The patent extracts stacked via structures from high-stress regions where they would experience delamination or cracking. By removing these structures from problematic locations under UBM features and relocating them to low-stress regions, the structural integrity is preserved while electrical connectivity functions are maintained.
Solution Approach 2:
The patent implements beforehand cushioning by establishing keep-out zones in advance of manufacturing, preventing the formation of stacked via structures in regions that would experience high tensile stress during thermal cycling. This proactive approach avoids the formation of structurally vulnerable configurations before stress conditions occur.
3Reliability
If conventional stacked via structures are used under UBM feature, then electrical connection is achieved, but high stress during thermal cycling causes failure
Solution Approach 1:
The patent extracts stacked via structures from the harmful high-stress environment under UBM features during thermal cycling. By relocating these structures to low-stress regions, the harmful thermal stress is eliminated from the via structures, preventing delamination and cracking while maintaining electrical connectivity functions.
Solution Approach 2:
The patent applies local quality by creating spatially varying via structure distributions that account for local stress conditions. Regions experiencing high thermal stress have no stacked vias (keep-out zones), while low-stress regions contain via structures. This localized optimization protects against thermal cycling damage while maintaining necessary electrical connections.
Data Source
AI summary
Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.