Stacked Via Package Substrate for IC Miniaturization
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Solution Overview
Problem
Conventional integrated circuit (IC) packages with stacked vias have limitations in size reduction and density due to the large widths or diameters of vias, which restrict the miniaturization of devices and the number of interconnects that can be formed.
Innovation Solution
The implementation of a package substrate with stacked vias, where a second via with a different shape is coupled to a first via, allowing for the formation of smaller overall vias with dimensions as small as 70-80 micrometers in width and 50-80 micrometers in height, enabling tighter and denser interconnects by using a seed layer and multiple vias to create a smaller diameter via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional single via structures are used, then the manufacturing process is simple, but the via width and diameter are large which limits device miniaturization
Solution Approach 1:
The patent divides a single via into multiple stacked vias (first via and second via) connected in series. Each via has a smaller cross-sectional area than a conventional single via, enabling reduced overall via width while maintaining electrical connectivity through the stack configuration.
Solution Approach 2:
The patent transitions from a single-plane via structure to a multi-layer stacked via structure by adding the vertical dimension. The first via and second via are positioned at different layers and connected through a via connection structure, effectively reducing the horizontal footprint while maintaining electrical function.
2Manufacturing precision
If via size is reduced to achieve tighter interconnect spacing, then device density increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
By segmenting the via into stacked components, the patent reduces the horizontal spacing requirements between interconnects. The vertical stacking allows tighter horizontal packing of interconnects on the package substrate, reducing overall device area while the segmentation enables each via component to be manufactured with standard precision tolerances.
3Productivity
If stacked vias with different shapes are used, then interconnect density and size reduction are achieved, but the manufacturing process complexity increases
Solution Approach 1:
The patent applies different geometric shapes to different via components based on their local functional requirements. The first via may have a cylindrical shape optimized for electrical connectivity, while the second via has a different shape (e.g., rectangular or tapered) optimized for mechanical support or alignment. This local optimization enables higher interconnect density while managing manufacturing complexity through shape differentiation where needed.
Data Source
AI summary
A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.