Stacked Via Seed Layer for Stress Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing defects and stress at via-to-via interfaces and void formation in stacked via structures during thermal cycles in Package-on-Package (PoP) technology, which affects the reliability and integration density of semiconductor devices.
Innovation Solution
The implementation of a seed layer as a diffusion blocking layer, comprising titanium and copper, between adjacently stacked vias, along with non-planar interfaces between metallization patterns, enhances the strength and reduces stress concentrations in stacked via structures without significantly increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a seed layer is added as a diffusion blocking layer between stacked vias, then reliability and stress resistance are improved, but manufacturing complexity and cost increase
Solution Approach 1:
A seed layer comprising titanium and copper is introduced as an intermediary diffusion blocking layer between adjacently stacked vias. This seed layer prevents copper diffusion from the vias into the dielectric material, thereby improving reliability and reducing stress concentrations at via-to-via interfaces without significantly complicating the manufacturing process
Solution Approach 2:
The seed layer is formed as a composite structure with multiple material layers (titanium and copper) to achieve both diffusion blocking functionality and electrical conductivity. This composite approach allows the structure to simultaneously prevent copper migration while maintaining the electrical pathways needed for device operation
2Quantity of substance
If stacked via structures are used to increase integration density, then component density is improved, but void formation and stress concentrations increase
Solution Approach 1:
The seed layer acts as a mediator between stacked vias, preventing direct contact between copper-rich via regions and the dielectric material. This intermediary layer eliminates the conditions that lead to void formation and stress concentrations, allowing high integration density to be achieved without the associated harmful effects
Solution Approach 2:
The introduction of the seed layer changes the material composition and interface properties at via-to-via boundaries. By modifying the chemical and physical parameters at these critical interfaces, the structure becomes more resistant to void formation and stress accumulation during thermal cycling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and stress at via-to-via interfaces, minimizes void formation, and improves the reliability and integration density of semiconductor devices, maintaining high performance while controlling costs.
Implementation Method 1
The implementation of a seed layer as a diffusion blocking layer, comprising titanium and copper, between adjacently stacked vias
Data Source
AI summary
In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.