Stacked VTFET Logic Gates With Shared Epitaxial Layers

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current semiconductor technologies face challenges in miniaturization and area scaling for vertical transport field-effect transistors (VTFETs), particularly in forming stacked structures that maintain effective width and reduce area occupancy while increasing device density and performance.

Innovation Solution

The development of stacked VTFET logic gate structures with shared epitaxial layers, where vertical fins have bottom, top, and shared epitaxial layers, and a connecting layer, allowing for a C-shaped connection between drain regions and enabling a 33% reduction in top-down area without sacrificing effective width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If stacked vertical FET structures are formed to increase device density, then area occupancy is reduced, but effective width is compromised

Engineering Contradiction:

Improvedevice densityVSAvoideffective width

Core Design Contradiction:

Quantity of substanceVSArea of moving object

Solution Approach 1:

The patent transitions from planar FET structures to vertically stacked FET structures, utilizing the third dimension (vertical stacking) to increase device density while maintaining the horizontal effective width through shared epitaxial layers that connect drain regions across multiple fins

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If conventional vertical FET structures are used, then manufacturing is simpler, but area occupancy is larger

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidarea occupancy

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges multiple FET structures by implementing shared epitaxial layers that are common to multiple vertical fins, allowing drain regions to be shared across adjacent fins and reducing the overall area occupancy while maintaining manufacturability through standardized formation processes

Inventive Principle:

Principle #5Merging (Combining)

3Area of stationary object

If stacked VTFET structures with shared epitaxial layers are formed, then area occupancy is reduced by 33%, but device complexity increases

Engineering Contradiction:

Improvearea occupancyVSAvoidstructure complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the FET structure into distinct vertical components (bottom epitaxial layer, top epitaxial layer, shared epitaxial layer) that can be formed through separate processing steps, allowing the complex stacked structure to be built systematically while achieving 33% area reduction through shared drain regions

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11810918B2Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers

Publication Date: 2023.11.07 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.