Stacked Wafer Reserve Wafer Repair for Yield Recovery
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Solution Overview
Problem
The yield of semiconductor stacked wafers decreases significantly as the number of wafers increases, necessitating an improved repair scheme to enhance production efficiency.
Innovation Solution
A semiconductor stacked wafer design incorporating a reserve wafer and a repair information block that allows for targeted repair of defective wafers and IO segments by replacing them with functional units from the reserve wafer, enabling repair at the die, pseudo channel, memory bank, or memory row levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of wafers in the stacked wafer is increased to achieve high bandwidth and large storage capacity, then the storage capacity and bandwidth are improved, but the yield of the stacked wafer drops sharply
Solution Approach 1:
The patent applies preliminary action by pre-configuring a reserve wafer that contains spare dies before the stacked wafer is assembled. This reserve wafer is prepared in advance to compensate for potential defects in the target wafer, allowing yield improvement without requiring additional wafers during operation. The repair information block is also pre-programmed with defect data to enable automatic defect compensation.
Solution Approach 2:
The patent uses copying by creating a reserve wafer that is a duplicate or copy of the target wafer structure, containing spare dies that can replace defective ones. The repair information block copies defect information from the target wafer to identify which spare dies should be activated, enabling yield improvement without increasing the total number of wafers.
2Quantity of substance
If the number of wafers is increased to improve storage capacity, then the storage capacity is improved, but the manufacturing complexity and difficulty of ensuring quality increase
Solution Approach 1:
The patent applies universality by designing the reserve wafer to serve multiple functions: it contains spare dies for defect compensation, includes the repair information block for defect management, and can be integrated with different target wafer configurations. This multi-functional design reduces the need for separate components, thereby reducing manufacturing complexity while maintaining high storage capacity.
Solution Approach 2:
The patent merges the reserve wafer and target wafer into a single integrated stacked wafer structure. The repair information block is integrated into the reserve wafer, combining defect management functionality with the spare die storage. This consolidation reduces the number of separate components and simplifies the manufacturing process while enabling high storage capacity through wafer stacking.
3Reliability
If a reserve wafer is added to repair defective wafers, then the yield is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the stacked wafer into distinct functional segments: the target wafer containing operational dies, the reserve wafer containing spare dies, and the repair information block containing defect data. This segmentation allows each component to be optimized independently and simplifies the repair process by clearly defining the roles of each segment, thereby reducing overall structural complexity while improving yield.
Solution Approach 2:
The patent uses the repair information block as an intermediary between the target wafer and the reserve wafer. This intermediary component stores defect information and controls the activation of spare dies, mediating the repair process without requiring direct complex interactions between the target and reserve wafers. This intermediary simplifies the overall system architecture while enabling effective yield improvement.
Data Source
AI summary
A semiconductor stacked wafer includes a plurality of wafers, a reserve wafer and a repair information block. Each of the wafers may include a plurality of dies, and the wafers including a logic wafer having a plurality of logic dies. The reserve wafer is configured to repair a target wafer among the wafers in accordance with a repair enable signal and repair information signals. The repair information block is located in the reserve wafer or the logic wafer, and the repair information block inputs input signals, and output the repair enable signal and the repair information signals in accordance with the input signals.