Stacked Word Line Grouping for Semiconductor Memory Integration

The patent merges word lines across multiple memory blocks by defining a memory block group where first memory blocks and second memory blocks share common word lines. Specifically, word lines in the first memory blocks are electrically connected to corresponding word lines in the second memory blocks, allowing a reduced number of physical word lines to control memory cells across multiple blocks. This combining approach increases integration density without proportionally increasing the number of lines required.

The patent implements multi-functionality in the peripheral circuits by designing voltage generation circuits that can generate voltages for multiple memory blocks simultaneously. The row decoder is configured to control word lines across first and second memory blocks using a reduced set of decoded signals. This universal approach allows peripheral circuits to serve multiple memory blocks without requiring separate dedicated circuits for each block, thereby reducing overall peripheral circuit complexity while maintaining high integration density.

The patent segments the memory device into memory block groups containing first memory blocks and second memory blocks with different word line configurations. This segmentation allows for standardized manufacturing of each block type while achieving high overall integration through their combination. The segmented approach simplifies the manufacturing process by enabling modular production and assembly, rather than requiring complex monolithic structures with an excessive number of unique word lines.