Stacking Identical Memory Chips Above ICs for Parallel Data Transfer
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Solution Overview
Problem
Current die stacking techniques for memory chips above integrated circuit chips are costly and inefficient, leading to high manufacturing and assembly expenses, and do not facilitate streamlined design and fabrication processes.
Innovation Solution
Implementing a system where multiple non-volatile memory chips of the same size and capacity are mechanically and electrically attached to integrated circuit chips within a family, allowing for simplified assembly, reduced design complexity, and enhanced data transfer rates through parallel data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple different-sized memory chips are stacked above IC chips of the same product family, then memory capacity requirements can be met, but manufacturing and assembly costs increase due to design and fabrication complexity
Solution Approach 1:
The patent applies homogeneity by using identical memory chips across all IC chip variants in a product family. Instead of designing and fabricating multiple sizes of memory chips to match different IC chip capacities, the invention uses a single standardized memory chip design that can be attached to any IC chip in the family, thereby reducing manufacturing and assembly costs while still meeting various memory capacity requirements through quantity variation.
Solution Approach 2:
The patent applies segmentation by allowing the memory capacity requirement to be met through stacking multiple identical memory chips rather than using a single large memory chip. This segmentation into multiple smaller units of the same design enables flexibility in meeting different capacity requirements while maintaining manufacturing simplicity through standardization.
2Quantity of substance
If multiple different-sized memory chips are stacked above IC chips of the same product family, then memory capacity requirements can be met, but design and fabrication complexity increases
Solution Approach 1:
The patent eliminates design and fabrication complexity by using homogeneous memory chip designs across the entire product family. All memory chips follow the same design specifications and fabrication processes, regardless of the IC chip variant they are attached to. This standardization dramatically reduces the complexity of designing and fabricating memory chips for different capacity requirements.
Solution Approach 2:
The patent applies universality by creating a memory chip design that serves multiple functions across different IC chip variants in the product family. A single memory chip design can be used with any IC chip in the family, making the memory chip universal and eliminating the need for variant-specific designs, thereby reducing overall design complexity.
3Ease of manufacture
If single memory chip is attached to each IC chip, then assembly process is simpler, but data transfer rates are limited
Solution Approach 1:
The patent applies segmentation by dividing the memory interface into multiple parallel channels, each connecting to a separate memory chip. Instead of using a single memory chip with a limited interface width, the system stacks multiple memory chips and utilizes multiple data buses to transfer data in parallel, thereby increasing data transfer rates while maintaining assembly simplicity through standardized attachment processes.
Solution Approach 2:
The patent transitions from a single-dimension data transfer approach to a multi-dimensional parallel transfer approach. By stacking memory chips vertically and establishing multiple independent data pathways, the system increases data transfer capacity without complicating the assembly process, as each chip follows the same attachment procedure.
Data Source
AI summary
Systems and methods for stacking a memory chip with respect to an integrated circuit (IC) chip are described. In the systems and methods, a plurality of like memory chips are stacked above one or more IC chip members of a family. The use of a plurality of like memory chips for the family may save costs and complications involved in designing, fabricating, and assembling memory chips of different sizes. The use of a plurality of the memory chips on a single IC chip can enable higher data transfer rates due to parallel data transmission.