Staged Counter Circuit for Real-Time Memory Row Counting
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Solution Overview
Problem
Existing memory technologies lack an efficient counter circuit capable of supporting advanced counting functions, such as real-time counting and flexible design, which is essential for modern memory applications like DDR5 DRAM to withstand Row Hammer and improve Refresh Management.
Innovation Solution
A counter circuit comprising multiple stages of counting circuits that obtain and process carry signals and bit values based on addend signals and system clocks, allowing for binary representation of counting results without relying on multi-stage flip-flop structures, enabling flexible and efficient counting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-stage flip-flop structures are used for counting, then the counting function can be implemented, but the circuit complexity increases and design flexibility is reduced
Solution Approach 1:
The patent extracts the essential counting function from the traditional multi-stage flip-flop structure and implements it using a simplified circuit architecture. By removing unnecessary flip-flop stages while retaining the core counting capability through alternative circuit elements, the design achieves both reduced complexity and maintained functionality.
Solution Approach 2:
The patent creates a universal counting circuit structure that can perform multiple counting functions (up-counting, down-counting, modulo counting) through a single unified architecture. This multi-functional design eliminates the need for separate dedicated circuits for different counting modes, thereby reducing overall circuit complexity while enhancing design flexibility.
2Productivity
If traditional counter circuits are used, then basic counting can be performed, but real-time counting capability and timeliness are insufficient
Solution Approach 1:
The patent implements preliminary action by pre-configuring the counting circuit with optimized signal paths and pre-computed carry signals. The circuit prepares counting states in advance and uses lookahead mechanisms to predict and prepare for upcoming count transitions, thereby reducing actual counting time and improving real-time performance.
Solution Approach 2:
The patent replaces traditional mechanical-style sequential flip-flop counting with an optimized electronic circuit implementation that uses direct logic gates and carry-lookahead mechanisms. This substitution eliminates the sequential propagation delays inherent in traditional designs, achieving faster counting speed and better timeliness.
Data Source
AI summary
A counter circuit includes multiple stages of counting circuits corresponding to binary bits, each stage being configured to: obtain a carry signal and a this-time bit value according to an addend signal and a bit value currently output by the stage, output the carry signal to a next-stage counting circuit, latch the this-time bit value in response to a first clock and output same to an output terminal of the stage of counting circuit in response to a second clock. An output of the counter circuit is composed of bit values output by the multiple stages and is a binary representation of a counting result. An addend signal of a start-stage counting circuit is a high-level signal and an addend signal of a non-start-stage counting circuit is a carry signal output by an immediately previous stage. The first and second clocks are obtained based on division of a system clock.