Staged Scenario Generation for IC Verification
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Solution Overview
Problem
Current verification methods for complex integrated circuit designs, such as System-on-Chip designs, face inefficiencies in stimulus generation, controllability, reusability, and scalability as they progress from device level to system level, leading to increased complexity and resource consumption.
Innovation Solution
A staged scenario generation methodology is implemented, where atomic generators are constructed in a hierarchical order, allowing code reuse and constraint management through a callback mechanism to generate and inject scenarios across levels, enhancing controllability, scalability, and reusability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If direct signal/pin driving method is used, then the method is simple to implement, but it fails when implementing complex design protocols and is inefficient for stimulus controllability and reusability
Solution Approach 1:
The verification system is segmented into multiple hierarchical levels: device level, module level, and system level. Each level has its own stimulus generation capabilities, allowing complex protocols to be implemented by combining simpler components at different levels rather than requiring a monolithic complex generator.
Solution Approach 2:
Module level generators act as intermediaries between device level generators and system level verification. They provide transfer functions that enable stimulus to pass through multiple levels hierarchically, allowing complex protocol implementation while maintaining reusability and controllability at each level.
2Reliability
If direct bus functional module control is used, then the module can drive design ports per protocol, but the tasks and functions must be called repeatedly in a specific order making tests complex and reusability nonexistent
Solution Approach 1:
Test scenarios are segmented into reusable transaction classes that can be independently defined and then composed into complete test sequences. This allows protocol compliance to be ensured at the transaction level while reducing overall test complexity through modular composition.
Solution Approach 2:
Transaction classes are designed to be universal and reusable across multiple test scenarios and hierarchical levels. A single transaction class can be used in different contexts and combined with other transactions to form various test sequences, eliminating the need to rewrite test logic for each scenario.
3Productivity
If transaction level control is used, then transactions can be generated and sent to transactors, but the atomic generator usually generates random transactions using only one transaction class reducing stimulus controllability
Solution Approach 1:
The stimulus generation system is made dynamic and adjustable at multiple levels. Transaction sequences can be randomly generated for stress testing or deliberately constructed for specific verification objectives. The system can adapt its behavior based on verification needs, allowing both high productivity and fine-grained controllability.
Solution Approach 2:
Different transaction classes can be assigned different weights or probabilities in random generation, or completely deterministic sequences can be used when needed. This asymmetric approach allows the system to optimize for either randomness or controllability depending on the specific verification objective.
4Adaptability or versatility
If scenario level control is used, then scenarios can be generated with constraints, but the number of constraints to be coded and complexity increases as one moves from lower level to higher level
Solution Approach 1:
Constraints are segmented and applied at appropriate hierarchical levels rather than all at once at the system level. Device level constraints handle low-level signal requirements, module level constraints handle protocol-specific requirements, and system level constraints handle overall test objectives. This distribution reduces the complexity at any single level.
Solution Approach 2:
Constraints are prepared and validated at lower hierarchical levels before being combined at higher levels. This preliminary action ensures that constraints are consistent and compatible before integration, reducing the overall complexity of constraint management and avoiding conflicts that would require complex resolution logic.
5Reliability
If moving from device level to system level verification is performed, then comprehensive verification is achieved, but reusability of test infrastructure becomes difficult and overall complexity increases
Solution Approach 1:
The verification infrastructure is segmented into hierarchical levels where each level can be independently developed and reused. Device level test infrastructure can be reused in module level verification through transfer functions, and module level infrastructure can be reused in system level verification, maintaining reusability across the entire verification hierarchy.
Solution Approach 2:
Test infrastructure is nested hierarchically with device level generators nested within module level generators, which are nested within system level generators. This nested structure allows lower level infrastructure to be reused at higher levels while maintaining the ability to add higher level functionality, achieving both verification completeness and reusability.
Data Source
AI summary
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.