Staged Word Line Charging Circuit for Lower Memory Power
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Solution Overview
Problem
The continuous application of a constant voltage for charging word lines or bit lines in memory devices increases power consumption, necessitating a solution to reduce power consumption in these charging processes.
Innovation Solution
A method of charging word lines or bit lines with various constant voltages applied in multiple stages, utilizing a first and second charging terminal to supply different voltages based on predefined reference conditions, with the second voltage starting after the first voltage meets a reference condition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a constant voltage is continuously applied to charge word lines or bit lines, then the charging capacity increases, but power consumption increases
Solution Approach 1:
The charging process is divided into multiple stages with different voltage levels. The first charging terminal applies a first voltage level, and the second charging terminal applies a second voltage level, segmenting the charging process to reduce overall power consumption while maintaining charging capacity
Solution Approach 2:
The voltage parameter is changed dynamically during the charging process. By switching between different voltage levels (first voltage and second voltage) at different charging stages, the system optimizes power consumption while ensuring complete charging of the word lines or bit lines
2Use of energy by moving object
If multiple charging terminals with different voltages are used, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The first charging terminal performs preliminary charging at a lower voltage level before the second charging terminal activates. This preliminary action reduces the overall power consumption by avoiding continuous high-voltage application, while the staged approach manages complexity through sequential operation
Data Source
AI summary
Disclosed is a memory device in which at least one word line or bit line is charged by a plurality of charging terminals. The memory device includes a first charging terminal for supplying a first voltage to the at least one word line or bit line, and a second charging terminal for suppling a second voltage to the at least one word line or bit line when voltage supply by the first charging terminal is completed. The supply of the second voltage starts when a charged voltage of the at least one word line or bit line, charged by using the first voltage, satisfies a first reference condition.