Staggered 3D Chip Packaging Without TSV
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional chip packaging technologies, particularly through the use of the Through-Silicon-Via (TSV) process, are complex and costly, limiting their adoption due to high investment costs and process complexity.
Innovation Solution
A staggered three-dimensional chip packaging structure is developed, where multiple chips are stacked with metal connecting pillars and a packaging layer, eliminating the need for a substrate support and avoiding the TSV process, using pads and metal connecting pillars for electrical connections, and incorporating a rewiring layer and metal bumps for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the Through-Silicon-Via (TSV) process is used to achieve three-dimensional stacking of chips, then three-dimensional packaging is achieved, but the process becomes complex, difficult, and expensive
Solution Approach 1:
The patent extracts and eliminates the TSV process from the three-dimensional packaging system. Instead of creating holes through the silicon substrate, the invention uses surface-level pads and metal connecting pillars to achieve electrical connections, thereby removing the complex drilling, lining, and filling steps associated with TSV while maintaining 3D stacking capability
Solution Approach 2:
The patent inverts the conventional TSV approach by moving the electrical connection interface from the bulk silicon (through-substrate vias) to the surface level (pads and metal pillars). This inversion simplifies the manufacturing process while achieving the same functional goal of inter-chip electrical connectivity in a three-dimensional arrangement
2Adaptability or versatility
If the Through-Silicon-Via (TSV) process is used to achieve three-dimensional stacking of chips, then three-dimensional packaging is achieved, but the investment cost increases
Solution Approach 1:
The patent employs simpler, less expensive materials and processes compared to TSV. The metal connecting pillars and pads use conventional semiconductor fabrication techniques that are already widely implemented in the industry, avoiding the need for specialized high-cost equipment and materials required for TSV processing
Solution Approach 2:
The patent uses standard pad and metal layer structures that are already familiar and well-established in conventional semiconductor manufacturing. These structures can be replicated using existing fabrication tools and processes, rather than requiring new, expensive process development for TSV
3Device complexity
If multiple chips are stacked in a staggered structure with metal connecting pillars, then electrical connections are achieved without TSV, but the chips require hanging out from lower chips
Solution Approach 1:
The patent transitions from planar two-dimensional chip arrangement to three-dimensional staggered stacking. By utilizing the vertical dimension and offsetting chips horizontally, the invention achieves enhanced electrical connectivity and heat dissipation pathways while maintaining simplified surface-level connection structures
Data Source
AI summary
The present disclosure provides a three-dimensional chip packaging structure and a method of making thereof. The structure includes: a plurality of chips stacked to form a staggered structure, each chip has one end hanging out from a lower chip and another end exposed out and connecting to a pad disposed on the chip, metal connecting pillars formed on the pads, a packaging layer disposed on the metal connecting pillars and the chips, a rewiring layer formed on the packaging layer, and a metal bump formed on the rewiring layer. The structure and method making it do not involve the Through-Silicon-Via (TSV) process, which is commonly used to achieve three-dimensional stacking of chips but is costly at the same time. Instead, the structure and method adopt pads and metal connecting pillars for electric connection. Also, the packaging structure does not necessitate a substrate for support, which reduces the package size.